DFx Engineer

Samsung Electronics

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Quick summary

Work type
On-site
Location
Austin, TX
Salary
$180,200–$270,400 / yr
Employment
Full-time
Posted
15 days ago
Freshness
Confirmed live today
Closes
Dec 31, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $225k
$131k $285k
below market most similar roles pay here above market

This role pays more than 78% of similar roles. Most pay $158,337–$223,750 — the blue band above. At the midpoint, this role pays about $225k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 94 open roles on FindRole.

Listed pay typically runs $106,000–$174,500 across 85 roles with salary data.

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View all roles at Samsung Electronics

At a glance

TL;DR · DFx Engineer

The DFx Engineer joins the Design Implementation team to support the development of high-performance computing IP, specifically focusing on GPU and system interconnect projects. This role involves the entire spectrum of activities from defining DFT scan architecture to implementation and pattern generation for silicon debug. Key responsibilities include creating detailed implementation specifications, performing RTL creation, LINT, timing-constraints, and ATPG, and benchmarking test-coverage and test-time. The engineer must ensure optimal balance between coverage and execution efficiency while resolving silicon issues like test-escapes and yield loss. Required skills include expertise in RTL coding, STA, and Physical Design, with familiarity with multi-voltage and multi-clocking domains. The work addresses high test-coverage requirements for bleeding-edge process nodes within mobile and automotive semiconductor market segments.

What you'll do

  • Define DFT scan architectures that balance test coverage, test-time, and execution efficiency.
  • Create detailed implementation specifications for SOC-level interfaces, clock designs, and test modes.
  • Implement DFT scan through RTL creation, LINT, timing-constraints, ATPG, and simulation.
  • Benchmark test-coverage and test-time to ensure they meet project expectations.
  • Explore new tools and methods to improve test-coverage and execution efficiency.
  • Resolve silicon issues, including test-escapes and yield loss, with SOC and Product Engineering teams.
  • Perform post-silicon debugging to analyze silicon behavior and test-escape issues.

What we're looking for

  • Must have a Bachelor’s degree with 10+ years of experience, a Master’s with 8+ years, or a PhD with 6+ years of experience.
  • Must have 10+ years of DFx expertise encompassing multiple tapeouts for digital IP (CPU/GPU) and/or SOC projects.
  • Must demonstrate the ability to architect DFT solutions from scratch and create detailed implementation specifications.
  • Must have a detailed understanding of test-coverage requirements across various scan modes for bleeding-edge process nodes.
  • Must have strong familiarity with RTL coding and STA with working knowledge of Physical Design.
  • Must have strong post-silicon experience debugging silicon behavior and test-escape issues.
  • Must be authorized to access information subject to U.S. export control laws.
  • Familiarity with multi-voltage and multi-clocking domain implementation is a plus (preferred).

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