DFT CAD Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$277,600 / yr
Posted
87 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $210k
This role $214k
$135k $293k
below market most similar roles pay here above market

This role pays more than 57% of similar roles. Most pay $177,250–$241,750 — the blue band above. At the midpoint, this role pays about $214k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3595 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2772 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · DFT CAD Engineer

Role Posting Log in to save

As a DFT CAD Engineer within the CAD and Methodology team of the Silicon Engineering Group, you will support the development of breakthrough custom silicon and hardware technologies. You will be responsible for the complete DFT and ATPG CAD solution for all design projects, which includes developing and implementing DFT and ATPG flows and participating in DFT architecture development. Your daily work involves verifying DFT implementations with the Synthesis CAD team, supporting infrastructure to generate structural test vectors, and analyzing coverage. You will address STA, physical, power, and logical issues while driving vendor engagements. Required skills include proficiency in Tcl, Perl, and Python scripting, along with experience in logic synthesis, scan architecture, scan compression, IEEE 1500 core wrapping, scan stitching, and DRC rule checking.

Skills

DFT ATPG Tcl Python Perl Verilog VHDL JTAG MBIST IEEE 1500 Scan Compression Logic Synthesis STA DRC Waveform Debugging Simulators

What you'll do

  • Develop and implement DFT and ATPG flows for all design projects.
  • Participate in the development and implementation of DFT architecture with the design team.
  • Verify DFT implementations in coordination with the DFT and Synthesis CAD team.
  • Support tools and infrastructure to generate structural test vectors and improve coverage.
  • Resolve STA, physical, power, and logical issues with DFT designers.
  • Drive engagements with DFT and ATPG vendors.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 3+ years of industry experience.
  • Proficiency in Tcl, Perl, and Python scripting.
  • Experience with industry-standard DFT and logic synthesis tools.
  • Familiarity with scan architecture, scan compression techniques, scan stitching, and scan reordering.
  • Familiarity with IEEE 1500 core wrapping.
  • Experience with DFT setup, rule checking (DRC), and debug.
  • Knowledge of ATPG, JTAG, MBIST, Verilog, VHDL, and waveform debugging tools (preferred).

Related searches

More DFT CAD Engineer jobs DFT CAD Engineer jobs in Cupertino All jobs at Apple Inc

More like this

Similar roles

DFT CAD Engineer

Apple Inc

Cupertino, CA 87 days ago $184,700–$324,800
DFT ATPG Tcl Python Perl Verilog VHDL JTAG MBIST IEEE 1500 Scan Compression Logic Synthesis STA DRC Waveform Debugging Simulators
10+ yrs exp
Save

DFT CAD Engineer

Apple Inc

Austin, TX 87 days ago
DFT ATPG Tcl Perl Python Verilog VHDL JTAG MBIST IEEE 1500 Scan Compression Logic Synthesis STA DRC Waveform Debugging Simulators
3+ yrs exp
Save

DFT CAD Engineer

Apple Inc

Austin, TX 87 days ago
DFT ATPG Tcl Perl Python Verilog VHDL JTAG MBIST IEEE 1500 Scan Compression Logic Synthesis STA DRC Waveform Debugging Simulators
10+ yrs exp
Save

DFT Lead Engineer

Broadcom

San Jose, CA 61 days ago $143,800–$230,000
DFT ATPG Scan Insertion MBIST TCL Python C++ Verilog Tessent SSN TetraMax Fastscan Mentor TestKompress IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL STA SerDes DDR PCIe ATE Ruby Perl
10+ yrs exp
Save

Staff DFT Engineer

Arm Holdings

Austin, TX +1 48 days ago $198,100–$268,000
DFT Verilog TCL Perl ATPG Scan Compression Memory BIST JTAG IJTAG Logic BIST static-timing-analysis Cadence Synopsys Siemens DFT AMBA CoreSight RTL Gate Level Simulation Silicon Debug
10+ yrs exp Hybrid
Save

CPU DFT Engineer

Qualcomm

Santa Clara, CA 24 days ago $147,900–$221,900
DFT ASIC Design Verilog VHDL Mentor Tessent TCL Python Perl Shell Scripting JTAG ATPG Scan Compression MBIST LBIST IEEE 1500
2+ yrs exp
Save