DFT CAD Engineer

Apple Inc

Confirmed live yesterday Trusted

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Work type
On-site
Location
Austin, TX
Posted
87 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Similar $210k
$137k $277k
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This listing doesn't post a salary. Most similar roles pay $177,250–$241,750.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3595 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2772 roles with salary data.

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At a glance

TL;DR · DFT CAD Engineer

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JOB TITLE: DFT CAD Engineer As a member of the CAD and Methodology team within the Silicon Engineering Group, the DFT CAD Engineer works on breakthrough custom silicon and hardware technologies. This role involves developing and implementing DFT and ATPG flows, participating in DFT architecture development, and verifying implementations with the Synthesis CAD team. The engineer will support infrastructure to generate structural test vectors, analyze coverage, and address STA, physical, power, and logical issues. Key technical requirements include proficiency in Tcl, Perl, and Python scripting, along with experience in industry-standard DFT and logic synthesis tools. Candidates should possess familiarity with scan architecture, scan compression, IEEE 1500 core wrapping, and scan stitching. The role also requires knowledge of JTAG, MBIST, and debugging compressed ATPG patterns for various chipsets.

Skills

DFT ATPG Tcl Perl Python Verilog VHDL JTAG MBIST IEEE 1500 Scan Compression Logic Synthesis STA DRC Waveform Debugging Simulators

What you'll do

  • Develop and implement DFT and ATPG flows for all design projects.
  • Participate in the development and implementation of DFT architecture with the design team.
  • Verify DFT implementations in coordination with the DFT and Synthesis CAD team.
  • Support tools and infrastructure to generate structural test vectors and improve coverage.
  • Resolve STA, physical, power, and logical issues with DFT designers.
  • Drive engagements with DFT and ATPG vendors.
  • Debug Compressed ATPG patterns, MBIST, and JTAG/1500-related issues.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 3+ years of industry experience.
  • Proficiency in Tcl, Perl, and Python scripting.
  • Experience with industry-standard DFT and logic synthesis tools.
  • Familiarity with scan architecture, scan compression techniques, scan stitching, and scan reordering.
  • Familiarity with IEEE 1500 core wrapping.
  • Experience with DFT setup, rule checking (DRC), and debug.
  • Knowledge of ATPG, JTAG, MBIST, Verilog, VHDL, and synthesis tools (preferred).

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