DFT CAD Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$184,700–$324,800 / yr
Posted
87 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k
This role $255k
$130k $346k
below market most similar roles pay here above market

This role pays more than 92% of similar roles. Most pay $177,250–$241,750 — the blue band above. At the midpoint, this role pays about $255k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3595 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2772 roles with salary data.

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At a glance

TL;DR · DFT CAD Engineer

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The DFT CAD Engineer joins the CAD and Methodology team within the Silicon Engineering Group to support the development of custom silicon and hardware technologies. This role involves developing and implementing DFT and ATPG flows, participating in DFT architecture design, and verifying implementations with the Synthesis CAD team. Key responsibilities include supporting infrastructure to generate structural test vectors, analyzing coverage, and addressing STA, physical, power, and logical issues. The candidate must utilize Tcl, Perl, and Python scripting alongside industry-standard DFT and logic synthesis tools. Required expertise includes scan architecture, scan compression, IEEE 1500 core wrapping, scan stitching, and scan reordering. The role specifically addresses the technical challenges of DFT setup, rule checking, and debugging for various chipsets including applications processors and storage controllers.

Skills

DFT ATPG Tcl Python Perl Verilog VHDL JTAG MBIST IEEE 1500 Scan Compression Logic Synthesis STA DRC Waveform Debugging Simulators

What you'll do

  • Develop and implement DFT and ATPG flows for all design projects.
  • Participate in the development and implementation of DFT architecture with the design team.
  • Verify DFT implementations in coordination with the DFT and Synthesis CAD team.
  • Support tools and infrastructure to generate structural test vectors and improve coverage.
  • Resolve STA, physical, power, and logical issues with DFT designers.
  • Drive engagements with DFT and ATPG vendors.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 10+ years of industry experience.
  • Proficiency in Tcl, Perl, and Python scripting.
  • Experience with industry-standard DFT and logic synthesis tools.
  • Familiarity with scan architecture, scan compression techniques, scan stitching, and scan reordering.
  • Familiarity with IEEE 1500 core wrapping.
  • Experience with DFT setup, rule checking (DRC), and debug.
  • Knowledge of ATPG, JTAG, MBIST, Verilog, VHDL, and waveform debugging tools (preferred).

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