DFT Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $109,700–$175,500 / yr
Employment: Full-time
Posted: 63 days ago
Freshness: Confirmed live today
Closes: Dec 10, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k

This role $143k

$96k $241k

below market most similar roles pay here above market

This role pays less than 82% of similar roles. Most pay $158,037–$227,300 — the blue band above. At the midpoint, this role pays about $143k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · DFT Engineer

Role Posting Log in to save

The DFT Engineer will join the team to manage various aspects of design for test, including MBIST, scan insertion, ATPG, ATE pattern development, and yield analysis. The role involves working closely with ATE engineers on yield improvement, developing patterns, managing hand-off processes, and performing silicon debugging. Key responsibilities include block and chip-level DFT implementation, lint checking, and performing ATPG and pattern simulation. The candidate must possess a solid understanding of digital logic fundamentals and experience in RTL lint checking, scan compression, and MBIST architecture. Required technical skills include proficiency with the Mentor Tessent and Synopsys DFT and simulation tool suites, along with Perl or other scripting languages. This position focuses on solving technical problems during silicon bring-up and enhancing DFT design methodologies.

Skills

DFT MBIST Scan Insertion ATPG ATE Pattern Development Yield Analysis Silicon Debugging RTL Lint Checking Scan Compression Mentor Tessent Synopsys DFT Perl STA Constraint Development Digital Logic Simulation

What you'll do

Perform MBIST architecture design, logic insertion, and scan insertion using industry-standard tools.
Execute ATPG and pattern simulation for both MBIST and scan.
Develop ATE patterns and manage the hand-off process for production.
Perform silicon debugging and work with ATE engineers on yield improvement.
Conduct DFT lint checking and analyze simulation failures.
Implement block and chip-level DFT tasks during the design phase.
Participate in silicon bring-up and product development activities.

What we're looking for

Bachelor's degree in Engineering and 8+ years of related experience.
Master's degree and 6+ years of related experience.
Required experience in silicon bring-up and yield improvement.
Solid understanding of DFT techniques and digital logic fundamentals.
Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
Experience in MBIST architecture and insertion.
Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
Proficiency with Perl or other scripting languages.
Experience in STA constraint development in DFT modes (preferred).

Similar roles

DFT Architect

Amd

San Jose, CA 57 days ago $232,000–$348,000

DFT Scan Compression MBIST ATPG Verilog Tessent Streaming Scan Network SSN STA FPGA Post-Silicon Debug Oscilloscope Logic Analyser Synthesis Physical Design Firmware Digital Communication PHY High-Speed IO

Save

DFT Engineer

Broadcom

San Jose, CA 57 days ago $121,900–$195,000

DFT ATPG MBIST Tessent Scan IJTAG CMOS Semiconductor Manufacturing Lithography Etch Deposition CMP Implant Data Analytics Root Cause Analysis Failure Analysis Silicon Bring-Up Yield Enhancement

8+ yrs exp

Save

CPU DFT Engineer

Qualcomm

Santa Clara, CA 40 days ago $147,900–$221,900

DFT ASIC Design Verilog VHDL Mentor Tessent TCL Python Perl Shell Scripting JTAG ATPG Scan Compression MBIST LBIST IEEE 1500

2+ yrs exp

Save

Senior DFT Engineer

Nvidia

Santa Clara, CA 11 days ago $136,000–$218,500

DFT ATPG BIST Scan Compression Fault Modeling Fault Simulation Silicon Bring-up VLSI Scripting Oscilloscope Logic Analyzer SoC GPU RAS DPPM

5+ yrs exp

Save

DFT Engineer

Amd

Austin, TX 73 days ago $139,680–$209,520

DFT DFD SystemVerilog Verilog SystemC C++ UVM Tessent JTAG LBIST MBIST Scan ATPG ICL/PDL Static Timing Analysis Perl Ruby Makefile Shell ATE post‑silicon bring‑up RTL ASIC Verification

Hybrid

Save

DFT CAD Engineer

Apple Inc

Austin, TX 103 days ago

DFT ATPG Tcl Perl Python Verilog VHDL JTAG MBIST IEEE 1500 Scan Compression Logic Synthesis STA DRC Waveform Debugging Simulators

3+ yrs exp

Save