DFT Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $121,900–$195,000 / yr
Employment: Full-time
Posted: 33 days ago
Freshness: Confirmed live yesterday
Closes: Feb 27, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k

This role $158k

$109k most similar roles pay here $242k

This role pays less than 78% of similar roles. Most pay $162,000–$229,100 — the shaded band above. At the midpoint, this role pays about $158k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 172 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 125 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · DFT Engineer

Role Posting Log in to save

The DFT Engineer joins the Core Switching Group to support networking switches for traditional and AI data centers. This role focuses on driving defect reduction, optimizing wafer sort and final test, and maximizing yield across the product portfolio. Key responsibilities include ATPG and MBIST pattern generation, bringup, and debug; performing scan diagnostics and repair debug; and conducting root cause analysis by correlating electrical failures to fab metrology and process tool data. The engineer will also manage NPI silicon bring-up and develop automated dashboards using AI tools. Required expertise includes CMOS device physics, semiconductor manufacturing processes, and testability features like SCAN, MBIST, and bscan. Technical skills include the Mentor/Siemens DFT Tessent tool, pattern conversion for testers, and proficiency in data analysis software or scripting to identify process shifts and resolve yield excursions.

Skills

DFT ATPG MBIST Scan IJTAG Tessent Silicon Characterization Data Analytics Scripting Semiconductor Manufacturing Wafer Sort Final Test Root Cause Analysis Failure Analysis CMOS Lithography Etch Deposition

What you'll do

Generate, bring up, and debug ATPG and MBIST DFT patterns for networking switches.
Monitor wafer sort and final test yield to drive continuous improvement plans for cost targets.
Perform scan diagnostics and repair debug to resolve yield excursions.
Correlate electrical failures with fab metrology and process tool data to identify defect mechanisms.
Support early silicon evaluation by debugging test programs and validating DFT structures.
Develop automated dashboards and yield correlation models using AI tools and scripting.
Execute pattern conversion for testers and perform post-silicon characterization.

What we're looking for

Bachelor's Degree and 8+ years of related experience, or Master's Degree and 6+ years of related experience.
Deep understanding of CMOS device physics, semiconductor manufacturing processes, and electrical testing methodologies.
Knowledge of Testability techniques including SCAN, MBIST, bscan, digital logic domain, embedded memories, and PHY/IO’s.
Experience with Mentor/Siemens DFT Tessent tool for scan, MBIST, bscan, and IJTAG pattern generation and debug.
Post-silicon experience in pattern conversion for testers, pattern bring-up, debug, and silicon characterization.
Proficiency in data analysis software and languages to perform volume data analysis and correlate failures.
Strong pre/post silicon debugging, analytical, and independent problem-solving skills.
Experience with AI tools for quick script development (preferred).

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