CPU Core Staff DFT Engineer

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $200,000–$300,000 / yr
Posted: 21 days ago
Freshness: Confirmed live yesterday
Closes: Sep 11, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $220k

This role $250k

$150k most similar roles pay here $316k

This role pays more than 74% of similar roles. Most pay $184,900–$254,750 — the shaded band above. At the midpoint, this role pays about $250k versus about $220k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 474 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 474 roles with salary data.

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At a glance

TL;DR · CPU Core Staff DFT Engineer

Role Posting Log in to save

As a member of the Cores DFT Team, the CPU Core Staff DFT Engineer owns ATPG and DFT responsibilities for next-generation high-performance cores. This role involves collaborating with architecture, IP design, Physical Design, and Product engineering teams to achieve first pass silicon success. Daily responsibilities include debugging low coverage, resolving DRC violation fixes, managing complex test pattern issues, and supporting silicon bring-up activities. The candidate must be proficient in Verilog for logic design and comfortable in Linux environments using scripting languages like Perl and TCL. Required technical expertise includes ATPG (Stuck-At, At-Speed, Path-Delay), scan compression, JTAG, MBIST, LBIST, and IEEE standards such as 1149.1, 1500, and 1687. The role focuses on the critical domain of ensuring high-quality design through advanced test generation tools and flow development for complex designs on 7nm or smaller process nodes.

Skills

DFT ATPG Scan Compression Verilog Linux Perl TCL JTAG MBIST LBIST Tessent ATE IEEE 1149.1 Agentic AI

What you'll do

Own ATPG and DFT responsibilities for next-generation high-performance cores.
Debug low coverage issues and resolve DRC violations with efficient solutions.
Perform logic design using Verilog to support hardware development.
Troubleshoot complex test pattern issues and simulation failures.
Support silicon bring-up activities and participate in post-silicon debug.
Utilize scripting languages like Perl and TCL within a Linux environment.
Implement industrial DFT standards including JTAG, MBIST, and scan compression.
Validate DFT features on ATE for advanced process nodes.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay), and scan compression.
Proficiency in logic design using Verilog.
Comfort in Linux environments and experience writing/using scripting languages like Perl or TCL.
Knowledge of industrial standards and practices in DFT, including JTAG, MBIST, and IEEE standards (preferred).
Experience with Tessent Scan/ATPG flows (preferred).
Experience with 7nm or smaller process nodes (preferred).
Experience using Agentic AI to develop flows, debug issues, and compress timelines (preferred).

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