DFT Engineer

Amd

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$139,680–$209,520 / yr
Posted
74 days ago
Freshness
Confirmed live today
Closes
Aug 14, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $175k
$129k $238k
below market most similar roles pay here above market

This role pays less than 64% of similar roles. Most pay $158,037–$227,300 — the blue band above. At the midpoint, this role pays about $175k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · DFT Engineer

Role Posting Log in to save

DFT Engineer The DFT Engineer joins the team to define, design, and verify robust Design for Test and Design for Debug solutions for complex, high-performance SoCs. This role involves collaborating with architecture, RTL, firmware, and verification teams to integrate DFX features that enable efficient silicon validation, bring-up, and debug across the full product lifecycle. Key responsibilities include designing DFX logic, building test plan documentation, creating directed and random verification tests, and debugging test failures to resolve design defects. The candidate must utilize technologies including JTAG, LBIST, MBIST, Scan, and ATPG, while using the Tessent tools suite. Required skills include Verilog, SystemVerilog, SystemC, C++, UVM concepts, and scripting in Perl, Ruby, Makefile, or shell. The work focuses on solving technical challenges in advanced processor designs and post-silicon bring-up.

Skills

DFT DFD SystemVerilog Verilog SystemC C++ UVM Tessent JTAG LBIST MBIST Scan ATPG ICL/PDL Static Timing Analysis Perl Ruby Makefile Shell ATE post‑silicon bring‑up RTL ASIC Verification

What you'll do

  • Design and integrate DFX logic into complex high-performance SoCs.
  • Build comprehensive test plan documentation covering hardware, firmware, and software driver use cases.
  • Estimate time requirements for new feature tests and necessary test environment changes.
  • Build directed and random verification tests for DFX features.
  • Debug test failures to identify root causes and resolve design defects with RTL and firmware engineers.
  • Review functional and code coverage metrics to modify or add tests as needed.
  • Collaborate with architects and hardware engineers to define new DFX features for verification.

What we're looking for

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience with DFT (Design for Test) and DFD (Design for Debug) architecture, design, and verification (preferred).
  • Experience with JTAG, LBIST, MBIST, Scan, and ATPG (preferred).
  • Familiarity with the Tessent tools suite, including Scan and ATPG (preferred).
  • Experience with post-silicon bring-up (preferred).
  • Experience with Verilog, SystemVerilog, SystemC, and C++ (preferred).
  • Experience with UVM concepts and the SystemVerilog language (preferred).
  • Scripting language experience in Perl, Ruby, Makefile, and shell (preferred).

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