DFT Engineering Director

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$216,400–$324,600 / yr
Posted
5 days ago
Freshness
Confirmed live yesterday
Closes
Apr 28, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $228k
This role $270k
$151k $343k
below market most similar roles pay here above market

This role pays more than 77% of similar roles. Most pay $193,497–$262,600 — the blue band above. At the midpoint, this role pays about $270k versus about $228k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 580 open roles on FindRole.

Listed pay typically runs $147,900–$218,400 across 557 roles with salary data.

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At a glance

TL;DR · DFT Engineering Director

Role Posting Log in to save

The DFT Engineering Director joins the Digital ASIC Design Team to lead the implementation and verification of advanced DFT and DFD techniques for low power, multi voltage designs. This role focuses on deploying methodologies that reduce test costs, increase product quality, and enhance yield learning on leading edge process technologies. Daily responsibilities include DFT pattern generation, coverage analysis, debug, and running gate level simulations. The successful candidate will utilize industry standard techniques such as scan, MBIST, JTAG, Scan Compression, ATPG, and Fault Simulation. Required expertise includes knowledge of Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware fault models. The position requires proficiency with industry EDA ATPG and insertion tools to solve complex testing and debugging problems in the ASIC design domain.

Skills

DFT DFD Scan MBIST ATPG JTAG Fault Simulation Gate Level Simulation Scan Compression ASIC Design Verification multi voltage design Coverage Analysis

What you'll do

  • Implement and verify advanced DFT and DFD techniques for low power, multi-voltage designs.
  • Deploy DFT methodologies to reduce test costs and increase product quality.
  • Generate DFT patterns and perform comprehensive coverage analysis.
  • Run and debug gate level simulations for ASIC designs.
  • Perform MBIST insertion and validation for leading edge process technologies.
  • Execute pre-silicon and post-silicon DFT domain tasks.
  • Utilize industry EDA ATPG and insertion tools for scan compression and at-speed testing.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
  • 15+ years of industry experience in the implementation and verification of advanced DFT/DFD techniques for low power and multi voltage designs (preferred).
  • Understanding of core-based test methodology and scan isolation (preferred).
  • Knowledge of fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware (preferred).
  • Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation, and at-speed testing (preferred).
  • Experience with industry EDA ATPG and insertion tools, and DFT implementation including Scan/ATPG, MBIST insertion/validation, and coverage analysis (preferred).

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