Staff DFT Engineer

Arm Holdings

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TXSan Jose, CA
Salary: $198,100–$268,000 / yr
Posted: 38 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $233k

$148k most similar roles pay here $281k

This role pays more than 80% of similar roles. Most pay $176,600–$227,900 — the shaded band above. At the midpoint, this role pays about $233k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 106 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 106 roles with salary data.

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At a glance

TL;DR · Staff DFT Engineer

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Staff DFT Engineer The Staff DFT Engineer joins the Solutions group DFT team to implement design-for-test solutions for SoC products across the client, datacenter, automotive, and IoT markets. This role involves architecting, implementing, and validating innovative DFT techniques on SoCs and sub-systems while collaborating with RTL, Verification, Physical Implementation, and Test engineering teams from early investigation through tape-out and silicon characterization. Daily responsibilities include inserting DFT logic, running gate level simulations, generating ATPG patterns to resolve coverage issues, and managing timing requirements. The role requires expertise in Siemens, Cadence, or Synopsys tools, along with skills in Verilog RTL, TCL, and Perl. Key technical competencies include Streaming Scan Networks, scan compression, Memory BIST, JTAG/IJTAG, at-speed test, fault simulation, and silicon debug to ensure high-quality manufacturing for complex integrated circuits across various process technologies.

Skills

DFT Verilog TCL Perl ATPG Scan Compression Memory BIST JTAG IJTAG static-timing-analysis Cadence Synopsys Siemens DFT Tools AMBA CoreSight Silicon Debug Gate Level Simulation

What you'll do

Architect, implement, and validate innovative DFT techniques for SoCs and sub-systems.
Insert DFT logic into SoC designs and validate features using industry standard simulation tools.
Execute RTL, unit delay, and timing-annotated gate-level simulations.
Generate ATPG patterns and debug coverage issues to meet specific targets.
Develop and validate design-for-test timing requirements while reviewing reports and providing fixes.
Support DFT RTL insertion, synthesis, scan insertion, and static-timing-analysis during the implementation phase.
Participate in ATE targeted test patterns, validation, and silicon debugging.
Perform silicon characterization and validation in coordination with Test and product engineering teams.

What we're looking for

Bachelor's or Master's degree in Electronic Engineering, Computer Engineering, or a related field.
10+ years of experience in Design for Test.
Proficiency in core DFT skills including Siemens tools, SSN, scan compression, MBIST, JTAG/IJTAG, and ATPG.
Experience coding in Verilog RTL, TCL, and/or Perl.
Experience with Cadence and/or Synopsys DFT and simulation tools.
Familiarity with SoC architectures, multi-clock domains, and low power build practices (preferred).
Familiarity with Arm IP such as Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink, and CoreSight (preferred).
Experience in high performance builds, 2.5D/3D test, or datacenter chips (preferred).