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DFT/DFx Architecture & RTL Lead

Amd

Santa Clara, CA 22 days ago $232,000–$348,000
Actively hiring Confirmed live today High trust Above market
DFT DFx RTL Design Verilog SystemVerilog ATPG Siemens Tessent Synopsys VCS Verdi SpyGlass MBIST JTAG IJTAG ICL/PDL Scan Compression Gate-Level Simulation Post-Silicon Debug SoC SerDes Memory PHY

DFT Architect

Amd

San Jose, CA 57 days ago $232,000–$348,000
Actively hiring Confirmed live today High trust Above market
DFT Scan Compression MBIST ATPG Verilog Tessent Streaming Scan Network SSN STA FPGA Post-Silicon Debug Oscilloscope Logic Analyser Synthesis Physical Design Firmware Digital Communication PHY High-Speed IO