Design Verification Lead

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$200,000–$300,000 / yr
Posted
52 days ago
Freshness
Confirmed live yesterday
Closes
Jul 21, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $187k
This role $250k
$120k most similar roles pay here $319k

This role pays more than 91% of similar roles. Most pay $158,325–$216,062 — the shaded band above. At the midpoint, this role pays about $250k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Design Verification Lead

As a Design Verification Lead in the AECG Group, you will join the front-end design and integration team to deliver first-pass silicon success for next-generation PCIe and CXL-based IP solutions. You will collaborate with architecture, hardware design, and firmware teams to define and verify high-speed connectivity features. Your daily responsibilities include developing comprehensive verification plans, designing UVM verification environments including monitors and scoreboards, and creating directed and constrained-random tests to ensure functional coverage. You will drive automation, methodology improvements, and the adoption of AI-assisted tools. The role requires expertise in SystemVerilog, Verilog, Python, Perl, and object-oriented programming. You will work on complex IP architectures for FPGA and ASIC solutions, focusing on high-speed protocols like PCIe Gen6 and 400G Ethernet while navigating the full development lifecycle from planning through tape-out.

What you'll do

  • Define and verify new PCIe, CXL, and high-speed connectivity features with architecture and firmware teams.
  • Develop comprehensive verification plans covering feature interactions, hardware/software integration, and performance requirements.
  • Design and implement IP or subsystem-level UVM verification environments including monitors, scoreboards, and checkers.
  • Create directed and constrained-random tests to ensure high functional coverage and design quality.
  • Execute regressions and debug failures to achieve first-pass silicon success for next-generation solutions.
  • Drive verification automation and the adoption of AI-assisted tools to improve development efficiency.
  • Provide technical leadership and mentoring within geographically distributed teams.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Minimum 10 years of design verification experience using UVM methodology.
  • Expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
  • Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
  • Proficiency in scripting and automation using Python, Perl, or similar languages.
  • Experience working across the ASIC/FPGA development lifecycle from planning through tape-out.
  • Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams.
  • Knowledge of computer architecture, system-level design concepts, and AI-driven verification methodologies is a plus.

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