Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

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Work type
On-site
Location
Austin, TX
Posted
6 days ago
Freshness
Confirmed live yesterday

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How this pay compares to similar roles

Similar $188k
$126k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $159,562–$216,062.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

As a Design Verification Engineer, you will join the hardware team to ensure bug-free first silicon for SoC and IP designs. You will be responsible for all phases of pre-silicon verification, including establishing methodologies, developing test plans based on micro-architecture, and building scalable, portable verification environments. Your daily work involves creating stimulus, checkers, assertions, and trackers while managing coverage and sign-off for RTL freeze and tape-out. You will execute design bring-up, run regressions, and debug failures using SystemVerilog and UVM. The role requires proficiency in Python, Perl, or TCL, along with experience in gate level simulations, waveform viewers, and power-aware verification methodologies like UPF. Additionally, you will utilize LLMs to improve execution efficiency and quality while ensuring the integrity of complex components including serial protocols like PCIe or USB.

What you'll do

  • Develop detailed test and coverage plans based on the micro-architecture.
  • Establish scalable and portable verification methodologies for specific IP designs.
  • Build verification environments including stimulus, checkers, assertions, and trackers.
  • Execute design bring-up and regression testing to identify hardware bugs.
  • Debug test failures and resolve issues found during the verification process.
  • Track and report progress using metrics such as bug counts and coverage data.
  • Utilize LLMs and related technologies to improve verification efficiency and quality.

What we're looking for

  • Bachelor's degree in a technical subject area.
  • Minimum of 10 years of relevant industry experience or equivalent.
  • Deep knowledge of Object-Oriented Programming (OOP), SystemVerilog, and UVM.
  • Experience developing scalable and portable test-benches.
  • Proficiency with verification tools including simulators, waveform viewers, and coverage collection.
  • Experience using Large Language Models (LLMs) to improve verification efficiency and quality.
  • Knowledge of scripting languages such as Python, Perl, or TCL.
  • Experience with power-aware (UPF) or similar verification methodologies.

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