CPU Core RTL Design Engineer

Amd

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $178,400–$267,600 / yr
Posted: 110 days ago
Freshness: Confirmed live today
Closes: Jul 8, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k

This role $223k

$136k $282k

below market most similar roles pay here above market

This role pays more than 68% of similar roles. Most pay $168,500–$239,462 — the blue band above. At the midpoint, this role pays about $223k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · CPU Core RTL Design Engineer

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As a CPU Core RTL Design Engineer, you will join the central core RTL team to design and optimize next-generation high-performance processor cores for client, server, and AI platforms. You will be responsible for designing and implementing RTL for CPU core pipeline components, contributing to microarchitecture definitions, and analyzing performance, power, and timing characteristics. Your daily work involves collaborating with architecture, verification, and physical design partners to deliver optimized designs, debugging pre-silicon and post-silicon issues, and supporting synthesis and timing closure. The role requires expertise in Verilog, SystemVerilog, and modern out-of-order CPU architecture. You will utilize skills in logic design, load/store units, and scripting languages like Python and Tcl to solve complex technical challenges in high-speed processor pipeline development.

Skills

Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Power Management Post-Silicon Debug SoC Microarchitecture

What you'll do

Design and implement RTL for CPU core pipeline components and related logic.
Contribute to the microarchitecture definition for next-generation processor cores.
Analyze and improve performance, power, and timing characteristics of designs.
Support design verification, synthesis, timing closure, and physical design efforts.
Debug and resolve pre-silicon and post-silicon issues.
Contribute to scalable RTL methodologies, libraries, and best practices.

What we're looking for

Design and implement RTL for CPU core pipeline components and related logic.
Contribute to microarchitecture definition for next-generation processor cores.
Analyze and improve performance, power, and timing characteristics.
Support design verification, synthesis, timing closure, and physical design efforts.
Debug and resolve pre-silicon and post-silicon issues.
Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments (preferred).
Strong understanding of modern CPU architecture, especially out-of-order cores (preferred).
Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field (preferred).

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