CPU Core RTL Design Engineer

Amd

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$178,400–$267,600 / yr
Posted
64 days ago
Freshness
Confirmed live 2 days ago
Closes
Jul 8, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $223k
$144k most similar roles pay here $281k

This role pays more than 75% of similar roles. Most pay $175,000–$223,700 — the shaded band above. At the midpoint, this role pays about $223k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · CPU Core RTL Design Engineer

Role Posting Log in to save

As a CPU Core RTL Design Engineer on the central core RTL team, you will design and optimize next-generation high-performance processor cores for client, server, and AI platforms. You will be responsible for implementing RTL for core pipeline components, contributing to microarchitecture definitions, and improving performance, power, and timing characteristics. Your daily work involves collaborating with architecture, verification, and physical design partners to resolve complex technical challenges and support synthesis, timing closure, and post-silicon debug. The role requires expertise in Verilog and SystemVerilog for CPU, SoC, or ASIC environments, along with a deep understanding of out-of-order cores and load/store units. You will also utilize scripting languages like Python and Tcl while navigating the full product lifecycle to develop scalable RTL methodologies for cutting-edge processor technology across various computing platforms.

Skills

Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Timing Closure Python Tcl DFT Power Management Post-silicon Debug Place-and-Route

What you'll do

  • Design and implement RTL for CPU core pipeline components and related logic.
  • Contribute to the microarchitecture definition for next-generation processor cores.
  • Analyze and improve performance, power, and timing characteristics of designs.
  • Support design verification, synthesis, timing closure, and physical design efforts.
  • Debug and resolve pre-silicon and post-silicon issues.
  • Develop scalable RTL methodologies, libraries, and best practices.

What we're looking for

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field is preferred.
  • Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments.
  • Strong understanding of modern CPU architecture, specifically out-of-order cores.
  • Expertise in logic design and high-speed processor pipeline development.
  • Knowledge of power-efficient and low-power design techniques including timing and power optimization.
  • Familiarity with synthesis, place-and-route, and timing closure.
  • Experience debugging and optimizing designs in collaboration with performance and verification teams.
  • Familiarity with scripting languages such as Python or Tcl.

Related searches

More CPU Core RTL Design Engineer jobs CPU Core RTL Design Engineer jobs in Austin All jobs at Amd

More like this

Similar roles

CPU Core Architecture RTL Engineer

Amd

Fishkill, NY 11 days ago $200,000–$300,000
RTL Verilog CPU Architecture Microarchitecture ASIC SoC x86 ARM Synthesis static timing *analysis DFT DFD Power Management Perl Shell Tcl Floorplan Tapeout
Save

CPU Systems RTL Engineer

Qualcomm

Santa Clara, CA 12 days ago $167,100–$250,700
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Waveform Debugging Simulators Power Management Functional Verification Hardware Engineering Firmware
4+ yrs exp
Save

CPU RTL Methodology Engineer

Qualcomm

Santa Clara, CA +1 12 days ago $198,700–$298,100
RTL Verilog SystemVerilog Python TCL Perl Bash GIT CI/CD CAD Tools CPU Microarchitecture Hardware Design Automation Scripting
6+ yrs exp
Save

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 126 days ago $127,200–$190,800
RTL system Verilog Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Clock Domain Crossing Microprocessor Design Bus Interface Cache Linting LEC CLP GDS2 Synthesis
2+ yrs exp
Save

RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA +3 12 days ago $142,200–$213,400
RISCV RTL Design Verilog VHDL Microarchitecture Logic Design Power Management Python Perl Waveform Debugging Simulators Hardware Engineering System Architecture
2+ yrs exp
Save

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 43 days ago $167,100–$250,700
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution
4+ yrs exp
Save