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CPU Core RTL Design Engineer

Amd

Austin, TX 6 days ago $144,800–$217,200
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Cache Hierarchy TLB Branch Prediction
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CPU Core RTL Design Engineer

Amd

Austin, TX 110 days ago $178,400–$267,600
Actively hiring Confirmed live today Trusted Above market
Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Power Management Post-Silicon Debug SoC Microarchitecture
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