ASIC Design Engineer, Tools and Methodology Development

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$116,000–$189,750 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $153k
$102k most similar roles pay here $244k

This role pays less than 85% of similar roles. Most pay $171,125–$227,300 — the shaded band above. At the midpoint, this role pays about $153k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · ASIC Design Engineer, Tools and Methodology Development

Role Posting Log in to save

The ASIC Design Engineer, Tools and Methodology Development joins a specialized team to develop and deploy in-house tools and workflows supporting various engineering business units. This role involves taking ownership of tools that verify common design blocks used across all products while acting as a DevOps engineer for automated RTL generation by developing new features and maintaining operations. The candidate will build new workflows and methodologies to ensure smooth integration into diverse IP development environments. Key technical requirements include a solid understanding of digital design concepts, hands-on experience in Verilog, and proficiency in scripting using Python or Perl. Additionally, the role requires expertise in Unix/Linux shell scripting and Makefiles. Relevant domain knowledge includes ASIC verification, Clocks/Resets design, CDC related flows, and backend flows such as Synthesis and Timing to solve complex hardware integration challenges.

What does a ASIC Design Engineer earn?

Median $214000 from 51 postings across 9 companies.

See salary data

Skills

Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design

What you'll do

  • Develop and deploy in-house tools and workflows to support engineering business units.
  • Take ownership of tools that verify common design blocks used across all products.
  • Act as a DevOps engineer for automated RTL generation by developing new features.
  • Maintain efficient operations for existing users within the RTL generation workflow.
  • Build new workflows and methodologies to ensure smooth integration into various IP development environments.
  • Implement hardware designs using Verilog based on fundamental digital design concepts.
  • Develop automation scripts using Python, Perl, or Unix/Linux shell scripting.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 3+ years of proven experience (preferred).
  • Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
  • Proficiency in scripting using modern Python and/or Perl.
  • Experience with Unix/Linux shell scripting and Makefiles.
  • Strong ability to collaborate with multi-functional teams and effectively communicate technical details.
  • Prior experience in ASIC verification (preferred).
  • Knowledge of Clocks/Resets, CDC flows, or backend flows (Synthesis, Timing) (preferred).

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