ASIC Design Engineer, Tools and Methodology Development

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Employment: Full-time
Posted: 25 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $196k

$141k $240k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,500–$223,000.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · ASIC Design Engineer, Tools and Methodology Development

Role Posting Log in to save

The ASIC Design Engineer, Tools and Methodology Development joins the hardware design team to develop and deploy in-house tools and workflows supporting various engineering business units. The role involves taking ownership of tools that verify common design blocks used across all products while acting as a DevOps engineer for automated RTL generation. Key responsibilities include building new workflows and methodologies to ensure smooth integration into diverse IP development environments. Candidates must possess a Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering and have experience with Verilog, modern Python, Perl, Unix/Linux shell scripting, and Makefiles. The position addresses technical challenges in ASIC verification, including Clocks/Resets design, CDC related flows, and backend processes like Synthesis and Timing to support complex hardware development.

What does a ASIC Design Engineer earn?

Median $200450 from 52 postings across 8 companies.

See salary data

Skills

Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation CDC Synthesis DevOps Digital Design Hardware Design IP Development

What you'll do

Develop and deploy in-house tools and workflows to support engineering business units.
Take ownership of tools that verify common design blocks used across all products.
Act as a DevOps engineer for automated RTL generation by developing new features.
Maintain efficient operations for existing automated RTL generation users.
Build new workflows and methodologies to ensure smooth integration into various IP development environments.
Utilize Python, Perl, and Unix/Linux shell scripting to automate design tasks.

What we're looking for

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience).
3+ years of proven experience (preferred).
Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
Proficiency in scripting using modern Python and/or Perl.
Experience with Unix/Linux shell scripting and Makefiles.
Strong ability to collaborate with multi-functional teams and effectively communicate technical details.
Prior experience in ASIC verification (preferred).
Knowledge of Clocks/Resets design, CDC flows, and backend flows (preferred).

Similar roles

ASIC Design Engineer

Nvidia

Santa Clara, CA 71 days ago $116,000–$189,750

RTL Design Verilog Microarchitecture Logic Synthesis Timing Analysis Python Perl C/C++ VLSI Design Digital Systems Computer Architecture ASIC Design SoC Post-Silicon Validation Front-end Flow

2+ yrs exp

Save

ASIC Design Engineer, Hardware

Nvidia

Austin, TX 19 days ago $116,000–$189,750

RTL Design Verilog SystemVerilog Python Perl SoC Architecture CDC Synthesis VCS dc_shell GDB Debussy DFT Physical Design Object-Oriented Programming Performance Analysis Design Automation

2+ yrs exp Hybrid

Save

ASIC Design Engineer

Apple Inc

Sunnyvale, CA 60 days ago $184,700–$324,800

ASIC Design RTL Verilog System Verilog SoC Digital Design Synthesis Python Perl TCL AMBA AXI AHB APB power-gating CDC RDC Logic Equivalence Check Formal Verification

10+ yrs exp

Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 92 days ago

ASIC Design Verilog System-Verilog RTL Design VLSI Digital Systems Design Computer Architecture Synthesis Timing Analysis CDC Formal Equivalence Python Perl Tcl Make files DFT Mixed Signal Design Post-Si Bringup Agentic AI flows

3+ yrs exp Hybrid

Save

ASIC Design Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700

ASIC Design RTL Micro-architecture SoC DRAM DFI PHY Memory Subsystem Simulators System-on-a-Chip Architecture Research

Save

ASIC Design Engineer

Apple Inc

Santa Clara, CA 164 days ago $129,300–$194,700

ASIC Design RTL Micro-architecture SoC DRAM DFI PHY Memory Subsystem Simulators System-on-a-Chip Architecture Research

Save