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Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation CDC Synthesis DevOps Digital Design Hardware Design IP Development +9 more Show less

Python Static Timing Analysis (STA) PrimeTime Tempus ASIC VLSI RTL-GDSII Git Perforce GenAI LLMs Software Architecture EDA Tools +8 more Show less

ASIC Design RTL Functional Verification Formal Verification Physical Design Python Perl Make Shell Scripting AI Frameworks EDA Data Pipelines Agentic Flow Hardware Development Methodology +9 more Show less