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ASIC Design Verification Technical Leader

Cisco

San Jose, CA 29 days ago $186,900–$267,700
Actively hiring Confirmed live today High trust Above market
SystemVerilog UVM ASIC Verification Python Perl FPGA Cadence Palladium Siemens Veloce Synopsys ZeBu PCIe Ethernet CXL HBM DDR SoC Architecture Silicon Bring-up Post-Silicon Validation Regression Infrastructure
10+ yrs exp
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