ASIC Design Verification Engineer, Technical Leader

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
31 days ago
Freshness
Confirmed live yesterday
Closes
Nov 19, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $227k
$136k $282k
below market most similar roles pay here above market

This role pays more than 77% of similar roles. Most pay $168,500–$222,625 — the blue band above. At the midpoint, this role pays about $227k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 288 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 225 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer, Technical Leader

Role Posting Log in to save

The ASIC Design Verification Engineer, Technical Leader joins the Silicon One development organization within the Common Hardware Group. This role involves collaborating with verification engineers, designers, and hardware teams to verify the ASIC through simulation, emulation, and ASIC bring-up. Key responsibilities include maintaining and enhancing existing verification environments, constructing test benches with scoreboards, agents, sequencers, and monitors, and writing test plans to drive module verification closure. The engineer will ensure complete coverage by reviewing code and functional coverage while using AI tools to improve design verification processes. Required skills include SystemVerilog, UVM methodology, and Perl or Python scripting. Candidates should have experience with constrained random environments and complex block verification. Domain knowledge in protocols like PCIe, CXL, Ethernet, AHB/AXI, DDR, or MMU is preferred.

Skills

System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR MMU Veloce HAPS Formal Verification Simulation Emulation

What you'll do

  • Maintain and enhance existing design verification environments.
  • Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks.
  • Write test plans and develop test cases to drive module verification closure.
  • Debug regression failures and verify ASIC functionality in simulation, emulation, and during bring-up.
  • Implement and review code to ensure complete functional and code coverage.
  • Use AI tools to develop innovative methods and processes to improve design verification quality.

What we're looking for

  • Bachelor's degree with relevant experience or Master's degree with relevant experience.
  • Prior experience with SystemVerilog and UVM methodology.
  • Prior experience verifying complex blocks, clusters, and/or top level for ASIC/SoC.
  • Prior experience building test benches from scratch with hands-on experience with SystemVerilog constraints, structures, and classes.
  • Prior experience with functional coverage and constrained random DV environments.
  • Proficiency in Perl and/or Python scripting.
  • Strong domain experience in one or more protocols such as PCIe, CXL, Ethernet, AHB/AXI, DDR, or MMU (preferred).
  • Experience with Veloce/HAPS or formal verification (iev/vc formal) knowledge (preferred).

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