ASIC Design Verification Technical Leader

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Carlsbad, CAAllentown, PA
Salary
$166,300–$238,300 / yr
Employment
Full-time
Posted
32 days ago
Freshness
Confirmed live yesterday
Closes
Nov 17, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $202k
$139k $256k
below market most similar roles pay here above market

This role pays more than 50% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $202k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 288 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 225 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Technical Leader

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The ASIC Design Verification Technical Leader joins the Silicon One team to support the Silicon Photonics group. This role involves driving the verification of silicon photonics driver integrated circuits for next-generation 100/200/400G per Lambda solutions. Key responsibilities include defining verification methodologies and standards, leading block and chip level verification for high-speed IPs like SerDes XSR/PAM4 and D2D IP, and mentoring engineers. The successful candidate will debug complex silicon issues during bring-up and influence architecture for testability. Required technical skills include System Verilog, UVM, and scripting in Python, Perl, TCL, or Shell Scripts. Experience with Formal Verification, Verilog, and emulation platforms like Veloce or HAPS is preferred. The work focuses on optimizing optical transceivers and modules for high-performance networking and AI/ML workloads.

Skills

System Verilog UVM ASIC Design Verification Python Perl TCL Shell Scripts Verilog Formal Verification Veloce HAPS Ethernet UCIE UAL SPI I2C SerDes D2D PHY ODSP

What you'll do

  • Define and lead verification methodology and standards across multiple projects and sites.
  • Lead verification at the block and chip level for high-speed IPs and control functions.
  • Review specifications and participate in design reviews to influence architecture for testability.
  • Mentor and coach verification engineers to improve technical skills and execution.
  • Debug complex silicon and system-level issues during the bring-up phases.
  • Support post-silicon bring-up and optimize integration and performance.
  • Develop scalable, reusable, and coverage-driven verification environments using UVM.

What we're looking for

  • Bachelor’s degree in Electrical or Computer engineering with 8+ years of ASIC Design Verification experience.
  • Master’s degree in Electrical Engineering or Computer Engineering with 6+ years of ASIC Design experience.
  • PhD in Electrical Engineering or Computer Engineering with 3 years of ASIC Design Verification experience.
  • Experience in System Verilog, UVM, and verification methodologies.
  • Experience owning and delivering verification for large-scale SoCs or subsystems.
  • Experience leading verification teams or projects.
  • Experience in scripting and automation such as Python, Perl, TCL, or Shell Scripts.
  • Strong experience with UVM for developing scalable, reusable, and coverage-driven verification environments (preferred).

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