ASIC Design Floorplan Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Fort Collins, CO
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live today
Closes
Apr 27, 2027
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $189k
$137k $237k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $162,559–$216,250.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 298 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · ASIC Design Floorplan Engineer

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The ASIC Design - Floorplan Engineer joins the Custom Silicon Design Team to develop custom CMOS ASICs for AI, Cellular, Networking, Computing, and Storage products. This role focuses on chip-level physical architecture and integration for advanced ASICs operating at speeds exceeding 1 GHz using 3 nm and smaller process nodes. Responsibilities include defining top-level floorplan architecture, die size estimation, hierarchy definition, and partitioning. The engineer will drive macro placement, power grid design, clock distribution planning, and pin placement while balancing performance, power, and area targets. Key technical requirements include VLSI design principles, floorplanning, and experience with PLLs and timing-critical structures. Candidates must possess TCL scripting and Linux skills, with preferred proficiency in Python, Perl, or Ruby, and experience using Cadence physical design tools.

Skills

ASIC VLSI Floorplanning Physical Design TCL Python Perl Ruby Linux Cadence PPA Timing Closure IR/EM Analysis Power Grid Design Clock Distribution ECO Physical Verification

What you'll do

  • Define and optimize top-level floorplan architecture, including die size estimation and hierarchy definition.
  • Drive macro placement, power grid design, clock distribution planning, and pin placement.
  • Lead top-level timing closure, congestion analysis, and ECO implementation for tapeout readiness.
  • Coordinate with block owners to ensure smooth block-level to top-level convergence.
  • Apply physical verification, IR/EM analysis, and PnR knowledge to achieve signoff-quality results.
  • Contribute to design flow automation and methodology development for advanced process technologies.
  • Provide technical leadership and mentorship for new design initiatives and engineering methods.

What we're looking for

  • BS in Electrical or Computer Engineering with 12+ years of relevant experience.
  • MS in Electrical or Computer Engineering with 10+ years of relevant experience.
  • Strong foundation in VLSI design principles and ASIC physical design fundamentals.
  • In-depth experience with floorplanning, die partitioning, and hierarchical design.
  • Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
  • Strong experience with TCL scripting and Linux environments.
  • Proficiency in Python, Perl, or Ruby (preferred).
  • Experience with Cadence or equivalent physical design tools (preferred).

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