ASIC Floorplan Design Engineer

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $116,000–$189,750 / yr
Posted: 11 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k

This role $153k

$104k most similar roles pay here $231k

This role pays less than 75% of similar roles. Most pay $152,875–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · ASIC Floorplan Design Engineer

Role Posting Log in to save

As an ASIC Floorplan Design Engineer - New College Grad 2026, you will join a specialized team to design and implement leading SoCs and GPUs. You will collaborate with architects, design leads, physical design leads, and package leads to craft and optimize floorplans during early chip development stages. Your daily responsibilities include driving the area review process, identifying interconnect improvements, and solving timing and routing congestion issues through informed physical implementation decisions. Additionally, you will build tools and improve infrastructure to enhance chip area and execution speed. The role requires expertise in Verilog, SystemVerilog, Python, Perl, and C/C++. You must possess a strong background in VLSI or Computer Architecture, with specific experience in CAD methodologies, floorplanning, power and clock distribution, packaging, P&R, and timing closure to address complex hardware engineering challenges.

Skills

ASIC Floorplan VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design Timing Closure Clock Distribution Packaging

What you'll do

Develop and optimize floorplans during the early stages of chip development.
Drive the area review process to identify improvements in area, interconnect, and layout.
Resolve timing and routing congestion issues through early design and physical implementation decisions.
Build new tools and improve existing infrastructure to optimize chip area and execution speed.
Manage power and clock distribution across the SoC floorplan.
Implement physical design methodologies including packaging and P&R techniques.

What we're looking for

Master's degree in Electrical Engineering, Computer Science, or Computer Engineering is required or equivalent experience.
Candidates must have a deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
Experience with Verilog, SystemVerilog, or similar Hardware Verification Languages (HVL) is required.
Proficiency in CAD and physical design methodologies including flow and tool development is required.
Knowledge of chip floorplan, power/clock distribution, packaging, P&R, and timing closure is required.
Experience with Python, Perl, and C/C++ programming languages is required.
Strong communication and interpersonal skills are necessary for team collaboration.
Experience in driving development of large scale ASIC floorplans is a plus.

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