ASIC Floorplan Design Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$116,000–$189,750 / yr
Employment
Full-time
Posted
57 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $183k
This role $153k
$104k $231k
below market most similar roles pay here above market

This role pays less than 72% of similar roles. Most pay $152,875–$214,000 — the blue band above. At the midpoint, this role pays about $153k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · ASIC Floorplan Design Engineer

Role Posting Log in to save

JOB TITLE: ASIC Floorplan Design Engineer - New College Grad 2026 The ASIC Floorplan Design Engineer - New College Grad 2026 joins a global team to design and implement leading SoCs and GPUs. You will collaborate with architects, design leads, and package leads to craft and optimize floorplans during early chip development. Key responsibilities include driving area reviews, identifying interconnect improvements, and solving timing and routing congestion issues through early design decisions. You will also build tools and improve infrastructure to optimize chip area and execution speed. Required skills include a background in VLSI or Computer Architecture, experience with Verilog, System Verilog, and CAD physical design methodologies, and proficiency in Python, Perl, and C/C++. This role addresses technical challenges in power/clock distribution, packaging, P&R, and timing closure for high-performance computing products.

Skills

ASIC Floorplan Design VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design P&R Timing Closure Power/Clock Distribution Packaging

What you'll do

  • Develop and optimize floorplans during the early stages of chip development.
  • Drive the area review process to identify improvement opportunities for area and interconnects.
  • Solve timing and routing congestion issues by influencing early design and physical implementation decisions.
  • Build new tools and improve existing infrastructure to optimize chip area and execution speed.
  • Manage power and clock distribution and packaging requirements for the SoC.
  • Execute physical design methodologies including Place and Route (P&R) and timing closure.

What we're looking for

  • Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
  • Deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
  • Experience in Verilog, System Verilog, or similar HVL.
  • Experience with CAD and physical design methodologies, including floorplan, power/clock distribution, packaging, P&R, and timing closure.
  • Proficiency in Python, Perl, and C/C++ programming languages.
  • Strong communication and interpersonal skills.
  • Experience in driving development of large scale ASIC floorplan (preferred).

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