ASIC Design Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Fort Collins, CO
Salary
$61,900–$99,000 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live yesterday
Closes
Apr 27, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $80k
$42k $250k
below market most similar roles pay here above market

This role pays less than 99% of similar roles. Most pay $168,175–$223,000 — the blue band above. At the midpoint, this role pays about $80k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 298 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · ASIC Design Engineer

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The ASIC Design Engineer joins the Custom Silicon Design Team within the ASIC Products Division to develop custom CMOS ASICs for AI, Cellular, Networking, Computing, and Storage products. This role focuses on the physical implementation of high-performance ASICs using 3 nm and smaller process nodes operating at speeds exceeding 1 GHz. Key responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification for multi-hundred-million gate complexity designs. The engineer will utilize commercial and in-house EDA tools like Cadence Innovus, Synopsys ICC2, and PrimeTime. Required technical skills include VLSI design, CMOS logic, and digital circuit fundamentals. Proficiency in UNIX/Linux environments and TCL is required, with Python or Perl preferred. The work covers the complete ASIC design cycle from RTL to GDSII.

What does a ASIC Design Engineer earn?

Median $214000 from 52 postings across 9 companies.

See salary data

Skills

ASIC Design VLSI CMOS Physical Design Floorplanning Placement Clock Tree Synthesis Routing Timing Closure DRC LVS IR/EM Checks RTL to GDSII UNIX Linux TCL Python Perl Cadence Innovus Synopsys ICC2 PrimeTime

What you'll do

  • Contribute to the physical design implementation of large-scale ASICs with multi-hundred-million gate complexity.
  • Support floorplanning, placement, clock tree synthesis, routing, and timing closure.
  • Perform physical verification tasks including DRC and LVS checks.
  • Conduct timing analysis, power planning, and IR/EM checks.
  • Execute post-route optimization and block-level integration.
  • Utilize commercial and in-house EDA tools for design, implementation, and verification.
  • Develop design flow improvements, automation, and deep sub-micron methodologies.
  • Interface with customers and internal stakeholders to support technical discussions and design reviews.

What we're looking for

  • Bachelor’s degree in Electrical or Computer Engineering, or Master’s degree in Electrical or Computer Engineering.
  • Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
  • Familiarity with ASIC physical design concepts such as placement, routing, and timing.
  • Proficiency in UNIX/Linux environments.
  • Working knowledge of TCL.
  • Familiarity with Python or Perl (preferred).
  • Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime (preferred).
  • Excellent communication, collaboration, and problem-solving abilities.

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