ASIC Design Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$126,700–$190,100 / yr
Posted
72 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 28, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k
This role $158k
$115k most similar roles pay here $239k

This role pays less than 79% of similar roles. Most pay $162,000–$221,050 — the shaded band above. At the midpoint, this role pays about $158k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · ASIC Design Engineer

As an ASIC Design Engineer on the Integrated Wireless Technology team, you will work with WiFi (802.11x) technology and SOC infrastructure using best-in-class design and verification methodologies. You will be responsible for micro-architecture, RTL design, and development of new functional blocks, while managing subsystem and full-chip integration through the complete ASIC lifecycle from concept to tape-out. This role involves collaborating with various teams including verification, DFT, FPGA emulation, and implementation. Key technical requirements include experience in multi-domain clocking, Design linting, CDC analysis, and a solid understanding of AMBA bus protocols like AHB and APB. You must be proficient in Python and Perl. Additional preferred skills include ARM CoreSight architecture, AXI Bus protocol, PCIe or USB peripheral subsystems, low power design, chip interconnect implementation, and exposure to AI/ML based design methodologies.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

What you'll do

  • Design micro-architecture and RTL for new functional blocks and subsystems.
  • Manage the full ASIC lifecycle from initial concept through to tape-out.
  • Implement multi-domain clocking architectures and manage clock/power domain partitioning.
  • Perform design linting and CDC analysis to triage and close violations.
  • Integrate functional blocks into the larger SoC infrastructure.
  • Develop scripts using Python or Perl to support design workflows.
  • Implement low power designs and chip interconnects (NoC).

What we're looking for

  • Bachelor's degree in Science or Engineering with 2+ years of experience, Master's with 1+ year, or a PhD is required.
  • 5+ years of industry experience in ASIC design, micro-architecture, and design integration are required.
  • A strong background in SoC micro-architecture including specification, definition, and implementation of functional blocks is required.
  • Hands-on experience with multi-domain clocking implementation in SOCs is required.
  • Experience in Design linting and CDC analysis, including triage and closure of violations, is required.
  • Solid understanding of AMBA bus protocols, including AHB and APB, is required.
  • Proficiency in Python or Perl is required.
  • Experience with ARM CoreSight, AXI, PCIe/USB subsystems, low power design, NOC implementation, or AI/ML methodologies (preferred).

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