ASIC Design Engineer
Qualcomm
Quick summary
Market check
How this pay compares to similar roles
This role pays less than 79% of similar roles. Most pay $162,000–$221,050 — the shaded band above. At the midpoint, this role pays about $158k versus about $192k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
Most-posted roles
At a glance
As an ASIC Design Engineer on the Integrated Wireless Technology team, you will work with WiFi (802.11x) technology and SOC infrastructure using best-in-class design and verification methodologies. You will be responsible for micro-architecture, RTL design, and development of new functional blocks, while managing subsystem and full-chip integration through the complete ASIC lifecycle from concept to tape-out. This role involves collaborating with various teams including verification, DFT, FPGA emulation, and implementation. Key technical requirements include experience in multi-domain clocking, Design linting, CDC analysis, and a solid understanding of AMBA bus protocols like AHB and APB. You must be proficient in Python and Perl. Additional preferred skills include ARM CoreSight architecture, AXI Bus protocol, PCIe or USB peripheral subsystems, low power design, chip interconnect implementation, and exposure to AI/ML based design methodologies.
What does a ASIC Design Engineer earn in California?
Median $214000 from 47 postings across 8 companies.
Skills
What you'll do
What we're looking for
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