NoC Interconnect Design Engineer and Architect

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
43 days ago
Freshness
Confirmed live yesterday
Closes
Jan 26, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k
This role $144k
$100k most similar roles pay here $261k

This role pays less than 90% of similar roles. Most pay $168,500–$231,037 — the shaded band above. At the midpoint, this role pays about $144k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · NoC Interconnect Design Engineer and Architect

The NoC Interconnect Design Engineer and Architect joins the multi-disciplinary NoC bus team to manage everything from early product specification and analysis to final RTL delivery for SoCs. This individual will create micro-architecture bus component specifications, analyze performance results, deliver RTL, and run tool flows while evaluating new IPs and driving protocol deployments. The role involves defining system-wide guidelines for IP interoperability and supporting verification, silicon validation, and software teams. Key technical requirements include expertise in various bus protocols like AHB, AXI, and CHI, as well as knowledge of network on chip, synthesis tools, STA, Lint, and power tools. Candidates must perform architecture tradeoff analysis regarding performance, power, and area while troubleshooting RTL design, FPGA, and post-silicon debug. Familiarity with CPU architecture is also considered a significant advantage for this role.

What you'll do

  • Create micro-architecture specifications for bus components based on performance and power analysis.
  • Deliver RTL designs to the SoC team while managing associated tool flows.
  • Evaluate new IPs and drive the deployment of new bus protocols.
  • Define system-wide guidelines for IP interoperability and power interconnects.
  • Support verification and silicon validation teams during the integration process.
  • Collaborate with software teams to ensure successful deployment of interconnects.
  • Perform architecture tradeoff analysis regarding performance, power, and area.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design experience.
  • Master's degree in Science, Engineering, or a related field with 1+ year of ASIC design experience.
  • PhD in Science, Engineering, or a related field.
  • Strong knowledge of bus protocols such as AHB, AXI, and CHI.
  • Expertise in ASIC flow including synthesis, STA, Lint, and power tools.
  • Ability to perform architecture tradeoff analysis regarding performance, power, and area.
  • Experience with RTL design, FPGA, and post-silicon debug for troubleshooting and problem solving.
  • Familiarity with CPU architecture is preferred.

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