ASIC Design and Integration Engineer
Apple Inc
Quick summary
Market check
How this pay compares to similar roles
This role pays less than 90% of similar roles. Most pay $168,500–$231,037 — the shaded band above. At the midpoint, this role pays about $144k versus about $200k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
Most-posted roles
At a glance
The NoC Interconnect Design Engineer and Architect joins the multi-disciplinary NoC bus team to manage everything from early product specification and analysis to final RTL delivery for SoCs. This individual will create micro-architecture bus component specifications, analyze performance results, deliver RTL, and run tool flows while evaluating new IPs and driving protocol deployments. The role involves defining system-wide guidelines for IP interoperability and supporting verification, silicon validation, and software teams. Key technical requirements include expertise in various bus protocols like AHB, AXI, and CHI, as well as knowledge of network on chip, synthesis tools, STA, Lint, and power tools. Candidates must perform architecture tradeoff analysis regarding performance, power, and area while troubleshooting RTL design, FPGA, and post-silicon debug. Familiarity with CPU architecture is also considered a significant advantage for this role.
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Qualcomm
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Qualcomm