NoC Interconnect Design Engineer and Architect

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
14 days ago
Closes
Dec 16, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $144k
$101k most similar roles pay here $256k

This role pays less than 90% of similar roles. Most pay $167,512–$223,700 — the shaded band above. At the midpoint, this role pays about $144k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 533 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 513 roles with salary data.

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At a glance

TL;DR · NoC Interconnect Design Engineer and Architect

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The NoC bus team at Qualcomm Technologies seeks an experienced VLSI engineer to join their multi-disciplinary group responsible for early product specification and analysis through final RTL delivery in large-scale SoCs. The role involves identifying architecture bottlenecks, driving micro-architecture choices using performance and power analysis, and providing design guidelines for protocol compliance. Day-to-day tasks include creating bus component specifications, analyzing performance results, delivering RTL code, and supporting verification teams. Ideal candidates possess strong knowledge of bus protocols like AHB, AXI, CHI, synthesis tools, and ASIC flow, with experience in deploying IPs in large SoCs. They should also excel in architecture trade-off analysis, problem-solving, and communication, with a preference for familiarity with CPU architecture.

Skills

AHB AXI CHI network_on_chip architecture_tradeoff_analysis ASIC_flow synthesis STA Lint power_tools RTL_design FPGA_debug post_silicon_debug performance_power_area_tradeoff

What you'll do

  • Define micro-architecture for bus components considering performance, power, and area trade-offs.
  • Analyze performance results to identify architecture bottlenecks and drive micro-architecture choices.
  • Evaluate new IPs and drive the deployment of new protocols in SoC projects.
  • Provide design guidelines for IP compliance and best practices for interconnects.
  • Deliver RTL code and support verification and silicon validation teams throughout development.
  • Collaborate with software teams to ensure successful deployments of interconnect solutions.

What we're looking for

  • Strong knowledge of bus protocols such as AHB, AXI, and CHI.
  • Experience with architecture trade-off analysis in VLSI design.
  • Proficiency in ASIC flow tools including synthesis, STA, and power management.
  • Expertise in RTL design, FPGA debugging, and post-silicon validation.
  • Ability to define micro-architecture for bus components considering performance, power, and area constraints.
  • Excellent communication skills for collaboration with cross-functional teams.
  • Familiarity with CPU architecture is preferred.

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