ASIC Design Engineer

Nvidia

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Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$100,000–$166,750 / yr
Employment
Full-time
Posted
102 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $183k
This role $133k
$86k $233k
below market most similar roles pay here above market

This role pays less than 87% of similar roles. Most pay $152,875–$214,000 — the blue band above. At the midpoint, this role pays about $133k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · ASIC Design Engineer

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JOB TITLE: ASIC Design Engineer - New College Grad 2026 As a member of the CPU Logic Design Team, you will be responsible for the CPU on-chip interconnect network, coherency, and last-level caches. Your day-to-day tasks involve micro-architectural definition, writing high-performance and low-power RTL, logic debug, synthesis, and timing closure. You will also support verification and implementation while creating design documentation and assisting with timing closure of super units. The role requires expertise in Verilog and a deep understanding of the ASIC design flow, including RTL design, prototyping, DFT, timing analysis, floor-planning, ECO, and lab debug. You must possess a strong background in computer architecture, cache coherency, or high-speed interconnects. This position focuses on solving technical challenges within processor and high-performance semiconductor designs for various product lines.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

Verilog RTL Design ASIC Design Flow Logic Synthesis Timing Closure Computer Architecture Cache Coherency DFT Timing Analysis Floor-planning ECO Logic Debug high speed interconnects Prototyping Bring-up Lab Debug

What you'll do

  • Define micro-architectures for CPU on-chip interconnect networks, coherency, and last-level caches.
  • Write high-performance and low-power RTL code for specific chip units.
  • Perform logic synthesis and achieve timing closure for individual and super units.
  • Create and maintain comprehensive design documentation.
  • Partner with the verification team to ensure the correctness of designed units.
  • Work with the implementation team to meet area, performance, and power goals.
  • Support the overall design flow including prototyping, DFT, and lab debug.

What we're looking for

  • BS or MS Degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
  • Experience in processor or other related high performance semiconductor designs.
  • Expertise in Verilog is required.
  • Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, and lab debug.
  • Effective communication and interpersonal skills for working in a dynamic, global team.
  • Strong background in computer architecture, cache coherency, or high speed interconnects (preferred).
  • Successful track record of mentoring junior engineers and interns (preferred).

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