ASIC Design Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$181,100–$318,400 / yr
Posted
53 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $250k
$132k most similar roles pay here $338k

This role pays more than 92% of similar roles. Most pay $165,237–$216,250 — the shaded band above. At the midpoint, this role pays about $250k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer

The ASIC Design Engineer role at the cutting-edge hardware development team requires an experienced professional with a minimum of 10 years in the field following a Bachelor's degree. This senior-level position involves conducting architecture research and developing memory or highly interconnected system architectures, focusing on RTL/micro-architecture design. The ideal candidate will possess deep knowledge of high-performance memory subsystems, including DRAM controllers, PHY designs, DFI interfaces, and calibration/training algorithms. Key responsibilities include characterizing performance, comparing different systems, and documenting results for publication. Additionally, the role demands expertise in driving new memory system architectures from DRAM upwards, exploring trade-offs between system performance, area, and power consumption, and collaborating with the performance team to create simulators, models, and test suites for high-performance parallel computer architectures.

What you'll do

  • Conduct architecture research and development of advanced memory systems and highly interconnected system designs.
  • Design RTL/micro-architecture for high-performance memory subsystems including DRAM controllers and PHY architectures.
  • Characterize system performance, conduct comparison studies, and document findings for publication.
  • Drive the creation of new memory system architectures from DRAM upwards.
  • Develop memory hierarchies for high-performance parallel computer systems (SOC).

What we're looking for

  • Bachelor's Degree with at least 10 years of experience in ASIC design.
  • Experience in architecture research for memory or highly interconnected systems.
  • Proficiency in RTL/micro-architecture development and high-performance memory subsystems.
  • Knowledge of DRAM controllers, PHY designs, DFI interfaces, and calibration algorithms.
  • Ability to characterize system performance and document results effectively.

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