ASIC Design Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 144 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $192k

$139k most similar roles pay here $233k

This listing doesn't post a salary. Most similar roles pay $162,000–$221,050.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer

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As an ASIC Design Engineer, you will join a complex team focused on crafting upcoming products and solving hardware technology challenges. Your daily responsibilities involve writing microarchitecture and design specifications, designing and debugging complex logic designs, and integrating complex IPs into the SOC. You will support front end integration activities including Lint, CDC, Synthesis, and ECO while collaborating with specialists in verification, emulation, STA, and physical design to ensure high quality alongside software and systems teams. The role requires expertise in Verilog RTL Logic Design and experience managing multiple clock domains and asynchronous interfaces. Preferred skills include proficiency in system architecture, CPU and IP integration, power and clock management designs, and familiarity with scripting languages such as Perl, Python, or TCL to navigate the intricacies of the chip development process.

What does a ASIC Design Engineer earn?

Median $214000 from 51 postings across 9 companies.

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Skills

Verilog RTL SOC Design Lint CDC Synthesis ECO STA Physical Design Python Perl TCL Microarchitecture Asynchronous Interfaces

What you'll do

Write microarchitecture and design specifications for SoC components.
Design, implement, and debug complex logic designs using Verilog RTL.
Integrate complex IPs into the System on Chip (SoC).
Perform front-end integration activities including Lint, CDC, Synthesis, and ECO.
Manage power and clock management designs across multiple clock domains.
Handle asynchronous interfaces and system architecture integration.
Coordinate with verification, emulation, STA, and physical design teams to ensure quality.

What we're looking for

Bachelor of Science degree required.
Minimum of 10 years of relevant industry experience.
Experience in Verilog RTL Logic Design.
Experience writing specifications and converting them into designs.
Experience with multiple clock domains and asynchronous interfaces.
Proficiency in front end tools, methodologies, and all aspects of the chip development process.
Knowledge of system architecture, CPU & IP integration, and power/clock management designs.
Familiarity with scripting languages such as Perl, Python, or TCL.