ASIC Design Engineer

Apple Inc

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$277,600 / yr
Posted
37 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $214k
$132k most similar roles pay here $293k

This role pays more than 68% of similar roles. Most pay $162,000–$221,050 — the shaded band above. At the midpoint, this role pays about $214k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer

As an ASIC Design Engineer, you will join the hardware team to contribute to various aspects of SOC design. Your daily responsibilities include architecting solutions for power management, writing microarchitecture and design specifications for SoC level IPs, and designing, implementing, and debugging complex logic designs. You will integrate complex IPs into the SOC while supporting front end activities such as Lint, CDC, Synthesis, and ECO. This role requires collaboration with specialists in verification, emulation, STA, and physical design, as well as coordination with software and systems teams. Key technical skills include experience with multiple clock domains, asynchronous interfaces, and proficiency in front end tools. Preferred capabilities include knowledge of system architecture, CPU and IP integration, and scripting languages like Perl, Python, or TCL to solve complex hardware challenges.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

What you'll do

  • Architect solutions for SoC power management.
  • Write microarchitecture and design specifications for power management and other SoC level IPs.
  • Design, implement, and debug complex logic designs.
  • Integrate complex IPs into the SOC.
  • Perform front-end integration activities including Lint, CDC, Synthesis, and ECO.
  • Manage multiple clock domains and asynchronous interfaces.
  • Convert technical specifications into functional hardware designs.

What we're looking for

  • Bachelor of Science degree required.
  • Minimum of 3 years of relevant industry experience.
  • Experience managing a team of logic designers is preferred.
  • Experience writing specifications and converting them into designs is preferred.
  • Experience with multiple clock domains and asynchronous interfaces is preferred.
  • Proficiency in front end tools, methodologies, and all aspects of the chip development process.
  • Knowledge of system architecture, CPU & IP integration, and power/clock management designs.
  • Familiarity with scripting languages like Perl, Python, or TCL.

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