Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: ASIC Design and Integration Engineer Remove filter Clear all

8 of up to 20 (filtered)

ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 22 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL Verilog SystemVerilog ASIC Design Synthesis Timing Closure CDC RDC UPF AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist Hardware Security
10+ yrs exp
Save

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 32 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification CDC RDC PPA Micro-architecture Digital Design
Save

ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 32 days ago
Actively hiring Confirmed live 2 days ago Trusted
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization CDC RDC Formal Verification Simulation Micro-architecture
Save

ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 38 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist
3+ yrs exp
Save

ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 38 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Trusted Below market
RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-power Design Lint Netlist Hardware Security
Save

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 144 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Low trust Above market
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization PCIe FPGA Prototyping CDC RDC LINT LEC High-speed I/O Formal Verification Simulation
10+ yrs exp
Save

ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 144 days ago
Actively hiring Confirmed live yesterday Low trust
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization PCIe FPGA Prototyping CDC RDC LINT LEC High-speed I/O Formal Verification
10+ yrs exp
Save

ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 144 days ago
Actively hiring Confirmed live 2 days ago Low trust
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification High-speed I/O PCIe FPGA Prototyping CDC RDC LINT LEC Low-power Design
3+ yrs exp
Save