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Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 11 days ago $136,000–$218,500
Actively hiring Confirmed live today High trust Competitive pay
ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation
5+ yrs exp Hybrid
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ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 75 days ago $116,000–$189,750
Actively hiring Confirmed live today High trust Below market
ASIC Physical Design Logic Equivalence Checking Formal Verification Logic Synthesis Clock Domain Crossing MTBF Analysis ECO Generation Python Perl TCL Make Synopsys Cadence Hardware Architecture Timing Closure
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