ASIC Design and Integration Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $129,300–$194,700 / yr
Posted: 32 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $162k

$117k most similar roles pay here $242k

This role pays less than 74% of similar roles. Most pay $162,000–$216,562 — the shaded band above. At the midpoint, this role pays about $162k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer

Role Posting Log in to save

The ASIC Design and Integration Engineer joins the Silicon Engineering team to develop custom SoCs that drive performance and efficiency for various products. In this role, you will design and implement complex ASICs by developing RTL using SystemVerilog and performing synthesis. You will collaborate with cross-functional hardware and software teams to integrate digital designs into complex systems while engaging with simulation-based and formal verification teams to ensure robust validation. Your daily responsibilities include conducting timing analysis and power optimization to meet specific PPA goals, as well as creating detailed micro-architecture and design documentation. The role requires proficiency in SystemVerilog, RTL design, and synthesis methodologies. Additional knowledge of CDC and RDC is considered a plus for this position focused on the technical challenge of designing high-performance integrated circuits.

Skills

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification CDC RDC PPA Micro-architecture Digital Design

What you'll do

Design and implement complex ASICs using SystemVerilog.
Perform RTL synthesis for custom SoC designs.
Partner with verification teams to ensure robust design validation through simulation and formal methods.
Integrate digital designs into complex SoCs in coordination with hardware and software teams.
Conduct timing analysis to meet performance goals.
Perform power optimization to achieve specific PPA targets.
Create detailed micro-architecture and design documentation.

What we're looking for

Bachelor of Science degree required.
Experience with SystemVerilog, RTL design, and synthesis (preferred).
Coursework in ASIC design including RTL design and verification (preferred).
Hands-on experience with ASIC design tools and methodologies (preferred).
Knowledge in CDC and RDC (preferred).
Strong analytical and problem-solving skills.
Excellent communication and teamwork skills to work effectively in cross-functional teams.

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