ASIC Design and Integration Engineer

Apple Inc

Confirmed live today Low trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $129,300–$194,700 / yr
Posted: 78 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k

This role $162k

$117k $242k

below market most similar roles pay here above market

This role pays less than 76% of similar roles. Most pay $167,346–$220,375 — the blue band above. At the midpoint, this role pays about $162k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer

Role Posting Log in to save

The ASIC Design and Integration Engineer joins the Silicon Engineering team to develop custom SoCs that drive product performance and efficiency. The primary responsibilities involve the design and implementation of complex ASICs, specifically developing RTL using SystemVerilog and performing synthesis. The engineer will engage with simulation-based and formal verification teams to ensure robust design validation while collaborating with hardware and software teams to integrate digital designs into complex SoCs. Key tasks include conducting timing analysis and power optimization to achieve specific PPA goals and creating detailed micro-architecture and design documentation. Required technical skills include SystemVerilog, RTL design, and synthesis. Candidates should possess experience with ASIC design tools and methodologies, with knowledge of CDC and RDC being a plus for solving these hardware integration problems.

Skills

SystemVerilog RTL Design ASIC Design Synthesis Formal Verification Simulation Timing Analysis Power Optimization CDC RDC Micro-architecture PPA

What you'll do

Design and implement complex ASICs using SystemVerilog.
Develop RTL and perform synthesis for custom SoCs.
Engage with simulation and formal verification teams to validate designs.
Integrate digital designs into complex SoCs with hardware and software teams.
Conduct timing analysis and power optimization to meet PPA goals.
Create detailed micro-architecture and design documentation.

What we're looking for

Bachelor's degree in a relevant field.
Experience in ASIC design including RTL design and verification (preferred).
Hands-on experience with ASIC design tools and methodologies (preferred).
Proficiency in SystemVerilog, RTL design, and synthesis (preferred).
Strong analytical and problem-solving skills (preferred).
Excellent communication and teamwork skills to work effectively in cross-functional teams (preferred).
Knowledge in CDC and RDC (preferred).

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