ASIC Design and Integration Engineer

Apple Inc

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 32 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $189k

$141k most similar roles pay here $239k

This listing doesn't post a salary. Most similar roles pay $162,000–$216,562.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer

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The ASIC Design and Integration Engineer joins the Silicon Engineering team to develop custom SoCs that drive performance and efficiency for various products. In this role, you will design and implement complex ASICs by developing RTL using SystemVerilog and performing synthesis. Your daily responsibilities include collaborating with hardware and software teams to integrate digital designs into complex systems while engaging with simulation-based and formal verification teams to ensure robust validation. You will also conduct timing analysis and power optimization to achieve specific PPA goals while creating detailed micro-architecture and design documentation. The role requires proficiency in SystemVerilog, RTL design, and synthesis, along with knowledge of CDC and RDC. This position focuses on the technical challenge of designing high-performance integrated circuits and solving complex hardware integration problems within a sophisticated silicon environment.

Skills

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization CDC RDC Formal Verification Simulation Micro-architecture

What you'll do

Design and implement complex ASICs using SystemVerilog.
Perform RTL synthesis for custom SoC development.
Partner with verification teams to ensure robust design validation through simulation and formal methods.
Integrate digital designs into complex SoCs in coordination with hardware and software teams.
Conduct timing analysis to meet performance requirements.
Perform power optimization to achieve specific PPA goals.
Create detailed micro-architecture and design documentation.

What we're looking for

Bachelor of Science degree required.
Experience with SystemVerilog, RTL design, and synthesis (preferred).
Knowledge of ASIC design tools and methodologies (preferred).
Coursework in ASIC design including RTL design and verification (preferred).
Knowledge in CDC and RDC (preferred).
Strong analytical and problem-solving skills (preferred).
Excellent communication and teamwork skills to work effectively in cross-functional teams (preferred).