ASIC Core DFT Technical Lead

Cisco

Confirmed live yesterday Low trust
Remote

Quick summary

Work type
Remote
Location
San Jose, CAAustin, TXMaynard, MASeattle, WACarlsbad, CA
Salary
$186,900–$267,700 / yr
Posted
38 days ago
Freshness
Confirmed live yesterday
Closes
Sep 22, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k
This role $227k
$146k most similar roles pay here $281k

This role pays more than 73% of similar roles. Most pay $177,250–$230,400 — the shaded band above. At the midpoint, this role pays about $227k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Core DFT Technical Lead

Role Posting Log in to save

As an ASIC Core DFT Technical Lead within the Common Hardware Group, you will drive cutting-edge Design-for-Test strategies and pioneer custom IP solutions for complex networking hardware. You will bridge the gap between front-end RTL, physical design, and post-silicon validation to ensure elite quality and testability across bare die, stacked die, and new silicon device models. The role involves developing custom DFT logic and integrating IP while managing test architecture, methodology, and infrastructure. You will utilize Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan, and post-silicon debug. Required technical skills include experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime, alongside proficiency in System Verilog for logic equivalency checking and scripting in Tcl, Python, or Perl to solve complex hardware challenges within the Silicon One architecture.

Skills

ASIC DFT System Verilog Tcl Python Perl JTAG Scan BIST ATPG TestMax Tetramax Tessent PrimeTime Verilog RTL Logic Equivalency Checking

What you'll do

  • Drive Design-for-Test (DFT) strategies for complex ASICs to ensure high quality and testability.
  • Develop custom IP solutions and integrate them into the Silicon One architecture.
  • Bridge the gap between front-end RTL, physical design, and post-silicon validation.
  • Manage technical vision across bare die, stacked die, and new silicon device models.
  • Implement Scan and BIST architectures including memory BIST and boundary scan.
  • Utilize EDA tools such as TestMax, Tetramax, and Tessent for ATPG and design analysis.
  • Perform System Verilog Logic Equivalency checking and validate test-timing of the design.
  • Develop custom DFT logic and infrastructure using Tcl, Python, or Perl scripts.

What we're looking for

  • Bachelor's degree plus 8 years of related experience, or Master's plus 6 years, or PhD plus 3 years.
  • Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan, and post-silicon debug.
  • Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
  • Prior experience with System Verilog Logic Equivalency checking and validating the test-timing of the design.
  • Proficiency in Tcl and Python/Perl scripting languages.
  • Preferred experience in Verilog design for developing custom DFT logic and IP integration.
  • Preferred familiarity with functional verification, DFT CAD development, and Test Architecture methodology.

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