ASIC Board Design Engineer, System Lead, PCB Layout, Signal Integrity, and System Architecture

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Milpitas, CA
Salary
$194,600–$285,700 / yr
Employment
Full-time
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Jan 29, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $240k
$134k $302k
below market most similar roles pay here above market

This role pays more than 84% of similar roles. Most pay $168,425–$220,125 — the blue band above. At the midpoint, this role pays about $240k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 254 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 185 roles with salary data.

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At a glance

TL;DR · ASIC Board Design Engineer, System Lead, PCB Layout, Signal Integrity, and System Architecture

The ASIC Board Design Engineer – System Lead, PCB Layout, Signal Integrity, and System Architecture joins the Service Provider Routing Hardware Engineering team to develop next-generation high-performance routers. In this individual contributor role, you will define long-term hardware architecture, power-delivery strategies, and technology roadmaps for complex networking systems. You will lead multi-disciplinary initiatives from concept to production, serving as a senior escalation point for signal integrity, power integrity, and reliability issues. Key responsibilities include establishing design standards and guiding engineers through complex investigations. Required expertise includes hardware board design for PCIe, Ethernet, DDR, and SerDes, alongside proficiency in Cadence (Concept/Allegro), HyperLynx, ANSYS, and Keysight ADS. You will utilize advanced lab instrumentation like VNAs and high-bandwidth oscilloscopes to validate ultra-high-speed signaling and power distribution.

What you'll do

  • Define long-term hardware architecture, power-delivery strategy, and technology roadmaps for high-performance networking systems.
  • Lead multi-disciplinary hardware initiatives from early concept through product release and customer delivery.
  • Act as a senior escalation point for complex architectural, signal integrity, power integrity, and manufacturing issues.
  • Establish reusable methods, constraints, verification practices, and quality standards for board design.
  • Guide senior engineers through architecture reviews, design tradeoffs, and complex technical investigations.
  • Represent hardware engineering in executive reviews, strategic supplier discussions, and standards activities.
  • Drive technical decisions using simulations, laboratory evidence, and product data to assess business impact.

What we're looking for

  • Must live within commuting distance of the Milpitas, CA office and commute to the lab 5 days per week.
  • Bachelor’s in Electrical or Computer Engineering with 11+ years experience, Master’s with 7+ years, or PhD with 4+ years.
  • Experience in hardware board design and system architecture from concept through production for high-performance systems.
  • Experience with high-speed digital design, signal and power integrity, and reliability testing using Cadence tools and lab instrumentation.
  • Experience leading complex, multi-site, and cross-functional engineering initiatives with silicon vendors and contract manufacturers.
  • Experience with advanced networking systems, ASICs, FPGAs, high-speed memory, and multi-gigabit SerDes (preferred).
  • Experience in co-packaged optics, ultra-high-speed signaling, and next-generation power delivery (preferred).
  • Proficiency with Cadence (Concept/Allegro), HyperLynx, ANSYS, Keysight ADS, and Python for test scripts (preferred).

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