Hardware Engineering Technical Leader

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Milpitas, CA
Salary
$171,600–$245,000 / yr
Employment
Full-time
Posted
6 days ago
Freshness
Confirmed live yesterday
Closes
Dec 4, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k
This role $208k
$144k $256k
below market most similar roles pay here above market

This role pays more than 58% of similar roles. Most pay $166,513–$227,350 — the blue band above. At the midpoint, this role pays about $208k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 267 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 201 roles with salary data.

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At a glance

TL;DR · Hardware Engineering Technical Leader

The Hardware Engineering Technical Leader joins the Common Hardware Group to develop next-generation hardware for the Service Provider Routing Hardware Engineering team. This individual contributor role serves as a recognized technical leader, defining board-level architecture, technology choices, and power-delivery strategies for complex networking products like the Cisco 8000 Series routers. You will lead major hardware initiatives from requirements through manufacturing release, solving high-risk signal integrity, power integrity, and thermal challenges. Key responsibilities include mentoring engineers, participating in design reviews, and collaborating with silicon vendors and fabricators. Required expertise includes high-speed digital design, PCIe, DDR, SerDes, and advanced packaging. You will utilize tools such as Cadence Concept and Allegro, while applying skills in schematics generation, hardware validation using oscilloscopes, and Python test script creation.

What you'll do

  • Define board-level architecture, technology choices, and power-delivery strategies for complex networking products.
  • Lead major hardware initiatives from initial requirements and architecture through validation and manufacturing release.
  • Resolve high-risk technical challenges involving signal integrity, power integrity, reliability, thermal, and manufacturing.
  • Own the design and validation of specific hardware sub-systems to ensure they meet functional specifications.
  • Partner with silicon vendors, PCB fabricators, and contract manufacturers to manage technical tradeoffs and product execution.
  • Communicate technical risks, alternatives, and design recommendations to senior stakeholders.
  • Mentor engineers and establish practical design methods, verification strategies, and quality improvements.
  • Contribute to product-line technology roadmaps and participate in cross-functional technical investigations.

What we're looking for

  • Bachelor’s degree in Electrical or Computer Engineering with 7+ years of experience, Master’s with 5+ years, or PhD with 2+ years.
  • Experience with hardware board design and system-level development, including high-speed digital design, signal integrity, and power integrity.
  • Experience with hardware validation using lab equipment such as oscilloscopes, logic analyzers, and spectrum analyzers.
  • Experience taking board designs from concept through production, including schematics generation, layouts, and troubleshooting using Cadence Concept and Allegro.
  • Experience with networking, server, or high-performance embedded systems, including Ethernet, PCIe, DDR, SerDes, and thermal management.
  • Experience leading technical projects, partnering with silicon vendors and fabricators, and leading multi-site or cross-functional engineering teams.
  • Experience with networking products design (preferred).
  • Experience with co-packaged optics, near-packaged optics, or optical and signal-integrity budget analysis (preferred).

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