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Python C++ Perl Matlab Visual_Studio_Code Analog_Mixed_Signal_Modeling Simulation Verification Design_for_Test CI/CD Azure Git Docker Jenkins PostgreSQL MariaDB +11 more Show less

ServiceNow Python Terraform Ansible PowerShell JavaScript MariaDB RHEL Windows Cisco Network Services Orchestrator Agile Scrum SDLC RMF CI/CD Grafana Prometheus Kubernetes Docker Git Jira +16 more Show less

Cisco Juniper Brocade MPLS OSPF BGP VLANs 802.1q port-channels CCNP DoD 8140 IAT Level 2 network management tools firewalls LAN WAN VoIP SD-WAN Kubernetes Terraform Ansible Git Jira Confluence +18 more Show less

Domain-Driven Design Java Kafka REST GraphQL Hexagonal Architecture AWS Azure GCP CI/CD Datadog Prometheus Grafana Apache Hop Salesforce integration ETL ELT Authentication Authorization AI ML +17 more Show less

Adobe Experience Cloud AEM API design microservices integration architectures React DevOps CI/CD cloud platforms headless CMS Storybook Salesforce SAP Veeva Agile Martech stack data integration customer 360 +13 more Show less

Linux HPC Docker Singularity Apptainer PodMan RDMA PostgreSQL MySQL MongoDB GPU computing Networking protocols Job schedulers Parallel file systems CI/CD +10 more Show less

Figma Git CI/CD CLI SLOs SLAs Distributed Systems Cloud Infrastructure AI ML Metrics Messaging Logs Traces Service Topologies Dependency Graphs Flame Graphs High-Density Visualization Operational Awareness Troubleshooting Workflows +15 more Show less

HSPICE Python Perl TCL Spectre Cadence Virtuoso FinFET GAA SOI DRC LVS Design for Manufacturability Silicon Debug Voltage Scaling Power Gating Advanced Technology Nodes SRAM Compiler Development +12 more Show less

Verilog Synopsys Cadence MentorGraphics FPGA PCIe CXL NVMe AXI DDR4 DDR5 Ethernet Linux Windows Python Simulation Testbench CI/CD +13 more Show less

UVM SystemVerilog C++ Python Perl SoC IP verification FPGA emulation platforms AI accelerators microarchitecture computer architecture RTL debugging scripting languages +9 more Show less

UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD +5 more Show less

UVM SystemVerilog C++ Python Perl SoC IP verification FPGA emulation platforms AI accelerators Mentoring Debugging RTL Microarchitecture Computer architecture +10 more Show less

Verilog Synopsys Cadence MentorGraphics PCIe CXL NVMe AXI DDR4 DDR5 Ethernet FPGA Linux Windows Python Simulation TestBench CI/CD +13 more Show less

Virtuoso ICADV Calibre ICV Pegasus StarRC QRC HSPICE Spectre Linux Perl Tcl Awk Sed EDA FinFet GAA CI/CD +13 more Show less

ASIC RTL Verilog SystemC VHDL Python Perl Tcl CI/CD Git Linux ARM DDR UCIe AMBA DFT STA CDC Lint Synopsys Cadence Mentor Graphics ModelSim QuestaSIM +19 more Show less

UVM SystemVerilog C++ ASIC verification Verification flows Tools CI/CD Project management Risk mitigation Team leadership Silicon bring up Debugging +7 more Show less

SQL Python ACA SOBs PBTs SBCs Kubernetes AWS Terraform PostgreSQL CI/CD Git Jira Confluence Google Workspace Microsoft Office Suite Regulatory Filings Health Insurance Product Design Essential Health Benefits Metal Tiers Cost-Sharing Structures +16 more Show less

LLM-powered tools AI Design tools Code editors Cross-functional collaboration Systems thinking Prototyping User experience design Product direction High-growth consumer tech Marketplace products CI/CD +7 more Show less

Python Matlab CTH Sierra Zapotec ALE3D Ansys Autodyn LS-Dyna EPIC SolidWorks NX CAD CAD CI/CD +8 more Show less

Vendor Management Construction Project Lifecycle Pre-Qualification Process Vendor Evaluation Criteria RFP Engagements Scopes of Work (SOW) Proposal Review Vendor Performance Management Risk Management Key Performance Indicators (KPIs) Executive Reporting Cross-Functional Collaboration Global Vendor Ecosystem Construction Procurement Commercial Management Project Controls +11 more Show less