Staff Engineer, RTL Design

Samsung Semiconductor

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $163,000–$253,000 / yr
Posted: today

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $208k

$130k most similar roles pay here $266k

This role pays more than 64% of similar roles. Most pay $163,900–$219,425 — the shaded band above. At the midpoint, this role pays about $208k versus about $192k for comparable roles.

Based on 239 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

Most-posted roles

View all roles at Samsung Semiconductor

At a glance

TL;DR · Staff Engineer, RTL Design

Apply Now Log in to save

As a Staff Engineer in RTL Design at Samsung’s Memory Solutions Lab (MSL) in San Jose, CA, you will join the Datacenter Device Solutions Group to develop innovative data center and cloud technologies. Your responsibilities include microarchitecture design, developing high-performance RTL IPs for proof-of-concepts, lab bring-up and validation of IPs, researching next-generation memory and storage controller features, and collaborating with hardware/software architects on FPGA prototypes and feasibility studies. You will also assist in software development and debugging for Linux/Windows device drivers while contributing to value proposition studies and publishing papers. Ideal candidates have a B.S. or higher degree in Computer Engineering or Electrical Engineering with extensive experience in HDL development, Verilog coding, and using CAD tools like Synopsys, Mentor, and Cadence. Familiarity with FPGA design flows and protocols such as PCIe, CXL, NVMe, AXI, DDR4/5, and Ethernet is essential.

Skills

Verilog Synopsys Cadence MentorGraphics FPGA PCIe CXL NVMe AXI DDR4 DDR5 Ethernet Linux Windows Python Simulation Testbench CI/CD

What you'll do

Develop new RTL IP for high-performance proof-of-concepts.
Conduct lab bring-up, testing, and validation of RTL IPs.
Research next-generation memory and storage controller features.
Work on feasibility studies and innovative FPGA prototypes.
Assist in developing Linux/Windows device drivers and debugging.
Publish papers and file patents related to research findings.
Collaborate on value proposition studies for technology solutions.

What we're looking for

B.S. with 10 years or M.S. with 8 years of experience in RTL development.
In-depth background in HDL development, Verilog coding, and CAD tool usage.
Experience with FPGA design flows, synthesis, timing analysis, and bring-up testing.
Hands-on expertise in hardware board bring-up, server system integration, and software integration.
Familiarity with PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet protocols.
Strong verbal and written communication skills for cross-functional team collaboration.
Ability to meet aggressive project deadlines and work across organizational boundaries.

Similar roles

Senior Engineer, RTL Design

Samsung Semiconductor

San Jose, CA today $138,000–$206,000

Verilog Synopsys Cadence MentorGraphics PCIe CXL NVMe AXI DDR4 DDR5 Ethernet FPGA Linux Windows Python Simulation TestBench CI/CD

Save

Staff Engineer, RTL Memory Centric Computing

Samsung Semiconductor

San Jose, CA today $163,000–$253,000

Verilog SystemVerilog HLS Python CI/CD PostgreSQL Kubernetes Docker AWS Grafana Prometheus Terraform

Save

Staff/Sr. Staff RTL Design Engineer - QGOV

Qualcomm

San Diego, CA 94 days ago $164,000–$246,000

Verilog SystemVerilog RTL FPGA ASIC Python Perl PCIe UART I2C DDRx SPI USB ARM RISC-V Multi-Power-Domain Multi-Clock-Domain Scripting Automation Digital-Design-Tools

Save