Senior Staff Engineer, Design Verification

What you'll do

• Develop verification infrastructure and automation for build, simulation, regression, and triage processes.
• Lead the verification of IP blocks in AI accelerators by collaborating with architects and RTL engineers.
• Create testbenches and define verification scope and plans for functional and performance validation.
• Ensure comprehensive documentation of verification strategy and ease-of-use for test environments.
• Mentor junior engineers and work cross-functionally to debug failures across design, compiler, and simulation teams.

What we're looking for

• 15+ years of industry experience in SoC or IP verification and test bench development.
• Strong background in UVM, System Verilog, C/C++, and scripting languages like Perl/Python.
• Experience verifying logic from complex IP blocks to full system testing.
• Understanding of RTL and strong debugging skills across multiple levels of logic.
• Prior experience with computational logic, interconnect networks, memory systems preferred.
• Knowledge of microarchitecture in AI accelerators and familiarity with FPGA/emulation platforms.