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SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling +8 more Show less

Microprocessor Design DSP Architecture Systems Engineering Electrical Engineering Computer Engineering

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC IC Packages +6 more Show less

SystemVerilog UVM OVM Python C++ Verilog VHDL SystemC Perl Linux Makefiles Formal Verification Generative AI 3GPP DSP RTL Design +11 more Show less

ASIC RTL GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting SoC +5 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC +5 more Show less

FPGA VHDL ASIC CPLD UVM DO-254 DOORS Xilinx Vivado Microchip Libero Intel Quartus Lattice Diamond PCIe AXI SERDES DMA MIL-STD-1553 ARINC 429 ARINC 664 TSN Mentor Graphics +15 more Show less

FPGA VHDL ASIC CPLD UVM Xilinx Vivado Microchip Libero Intel Quartus Lattice Diamond DO-254 DOORS PCIe AXI SERDES DMA MIL-STD-1553 ARINC 429 ARINC 664 TSN Mentor Graphics +15 more Show less

SystemVerilog UVM RTL Design AMBA CHI PCIe Compute Express Link Formal Verification Python Perl Cache Coherence Memory Systems Bus Protocols Verification Methodology +8 more Show less

Verilog SystemVerilog UVM Python Tcl Perl Shell DFT STA RTL Design ASIC SoC FPGA Synopsys Cadence VCS PrimeTime GDS HBM PCIe +15 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling Coherent Interconnects +9 more Show less

Formal Verification SystemVerilog SVA Python C/C++ Perl UVM EDA Tools RTL Computer Architecture Graphics Pipelines Power Gating UPF JIRA Confluence Memory Subsystems +11 more Show less

RF Microwave Measurement VNAs Signal Generators Power Meters HALT HASS EMI EMC Vibration Qualification EVT NPI Test Automation +8 more Show less

SystemVerilog UVM RTL Design AMBA CHI PCIe Compute Express Link Formal Verification Python Perl Cache Coherence Memory Systems Bus Protocols Verification Methodology +8 more Show less