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LLM-powered applications Python JavaScript TypeScript React Node.js Docker Kubernetes CI/CD Git PostgreSQL MongoDB Vega D3 AWS Azure Google Cloud Platform GitHub Jira Slack Trello Confluence +17 more Show less

Perl TCL Shell Python Verilog GPU architecture SOC/ASIC design flow P&R tools Floor-planning PPA optimization Logical equivalence checking Timing constraints Scripting Programming +9 more Show less

HSPICE Python Perl TCL Spectre Cadence Virtuoso FinFET GAA SOI DRC LVS Design for Manufacturability Silicon Debug Voltage Scaling Power Gating Advanced Technology Nodes SRAM Compiler Development +12 more Show less

Verilog Synopsys Cadence MentorGraphics FPGA PCIe CXL NVMe AXI DDR4 DDR5 Ethernet Linux Windows Python Simulation Testbench CI/CD +13 more Show less

UVM SystemVerilog C++ Python Perl SoC IP verification FPGA emulation platforms AI accelerators microarchitecture computer architecture RTL debugging scripting languages +9 more Show less

UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD +5 more Show less

UVM SystemVerilog C++ Python Perl SoC IP verification FPGA emulation platforms AI accelerators Mentoring Debugging RTL Microarchitecture Computer architecture +10 more Show less

Python MATLAB ANSYS ABAQUS FEA COMSOL META CAD SolidWorks FiberSim NX Windchill Git JIRA Confluence CI/CD +11 more Show less

Python MATLAB ANSYS ABAQUS FEA COMSOL SolidWorks AutoCAD FiberSIM NX Windchill Jira Confluence Git Linux +10 more Show less

SRAM Register_File High_Performance_Design Low_Power_Design Semiconductor_Device_Fundamentals Variation_Aware_Simulation Custom_Memory_Layout NanoTime Ansys_EMIR_Analysis ESP_CV Liberate_Power_Analysis Verilog BIST DFT Memory_Analysis_Flow_Development +10 more Show less

Cadence_APD SiP High_speed_IO_interfaces IC_packaging_structures Electromagnetic_field_analysis Flip_chip_BGA 2_5D_Interposer 3D_Interposer Cadence_Allegro PCB_Editor Advanced_Package_Designer XtractIM PowerSI HFSS Q3D Calibre_tool Design_Rules_Check High_speed_layout_constraints DDR PCIe UCIE +16 more Show less

React TypeScript JavaScript CSS Git GitHub WCAG CI/CD Unit testing Visual regression testing Accessibility practices Responsive design AI-assisted development tools LLM powered applications Generative AI landscape Modern dev-ops practices +11 more Show less

Tcl Python Cadence_Innovus Place-and-route Physical_Design Timing_Analysis Physical_Verification EDA Automation CI/CD +5 more Show less

SiemensMentorXpedition Altium CadenceAllegroPCB Valor CAM350 DDR5 HDMI PCIe SATA MIPI USB2 USB3x GigE LPDDR MSOffice365Tools AIproblem-solving EMImitigationtechniques AgilePLMsoftware DesignforManufactureDFManalysis +14 more Show less

Verilog SystemVerilog UVM Git Vivado Palladium Zebu Veloce C++ Python Perl Linux AXI4-x DDRx PCIe JTAG DPI Simulation Emulation Formal Verification Static Verification +16 more Show less

Verilog SystemVerilog RTL FPGA ASIC Python Perl PCIe UART I2C DDRx SPI USB ARM RISC-V Multi-Power-Domain Multi-Clock-Domain Scripting Automation Digital-Design-Tools +15 more Show less

CadenceAllegro MentorExpedition SPICE PCIe LPDDR4x DDR4 DDR5 JTAG SMBus PMBus SPI BMC integration signal integrity power integrity oscilloscopes logic analyzers high-speed interfaces PCB design thermal management EMI shielding rack-level system integration regulatory compliance firmware architecture x86 FW/SW stack +20 more Show less