Staff/Sr. Staff Design Verification Engineer - QGOV

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$164,000–$246,000 / yr
Posted
94 days ago
Closes
Sep 15, 2026

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k
This role $205k
$149k most similar roles pay here $264k

This role pays more than 54% of similar roles. Most pay $174,200–$234,012 — the shaded band above. At the midpoint, this role pays about $205k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 763 open roles on FindRole.

Listed pay typically runs $151,900–$229,800 across 453 roles with salary data.

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At a glance

TL;DR · Staff/Sr. Staff Design Verification Engineer - QGOV

Join Qualcomm Technologies Inc.’s Design Verification team as a senior verification engineer, where you will develop scalable and portable verification methodologies for RTL designs in Verilog and SystemVerilog, focusing on hardware building blocks and standard interfaces like PCIe, DDR, USB, I2C, SPI. Your daily tasks include creating test plans, coding test benches, writing assertions, running simulations, and achieving coverage goals using UVM-based verification techniques. You will also explore innovative methodologies such as formal verification to enhance the quality and efficiency of your work. The role requires expertise in SystemVerilog, UVM/OVM, and experience with emulation platforms like Palladium and Zebu, along with a strong understanding of chip-level functional models and OOP concepts. Ideal candidates are self-starters who can develop and maintain CAD infrastructure for silicon design teams while collaborating effectively within the team.

What you'll do

  • Develop verification methodology for scalable and portable environments across simulation and emulation.
  • Create test plans to verify hardware building blocks and standard interfaces like PCIE, DDR, USB.
  • Own end-to-end DV tasks including coding test benches, writing assertions, and achieving coverage goals.
  • Explore innovative DV methodologies such as formal, simulation, and emulation-based techniques.
  • Develop and maintain an emulation environment to collect metrics related to the emulation process.

What we're looking for

  • 5+ years of RTL/FPGA design experience in Verilog and embedded system architecture
  • Extensive Design Verification experience with simulation and emulation flows
  • Strong System Verilog/UVM verification skills including assertion-based methodologies
  • Experience developing and maintaining scalable emulation environments
  • Knowledge of communication protocols like PCIe, DDRx, I2C, SPI
  • Familiarity with formal verification methodologies and tools
  • Proficiency in scripting languages such as Perl or Python for automation

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