Principal RTL Design Engineer - QGOV
Qualcomm
At a glance
AI generatedAs a Design Engineer at Qualcomm Technologies in San Diego, you will join a dynamic team responsible for developing advanced digital designs. Your daily tasks will include micro-architecture design, RTL development using Verilog and SystemVerilog, debugging during the development process, creating detailed documentation, optimizing designs for performance metrics, and collaborating with cross-functional teams such as DFT, Implementation, Verification, Emulation, and Firmware. Ideal candidates have 6 to 10 years of experience in RTL/FPGA design, a strong background in digital logic design, and expertise in SystemVerilog, Linting, CDC, Synthesis (FPGA and ASIC), and scripting languages like Python or Perl. The role involves working on complex digital interfaces such as PCIe, UART, I2C, DDRx, SPI, and USB, requiring knowledge of ISAs like ARM THUMB or RISC-V and experience with multi-power domain and multi-clock domain designs.
Skills
What you'll do
What we're looking for
Market check
This $164,000–$246,000 range sits above 61% of similar postings on FindRole.
Peer median band
$143,000–$244,000
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$168,500–$214,500
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 569 open roles on FindRole.
Listed pay typically runs $148,300–$224,400 across 536 roles with salary data.
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