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Synthesis STA TCL Formal Verification DC Genus Fusion Compiler CLP Timing Analysis FPGA DSP Hardware Engineering +7 more Show less

SoC Architecture CPU Microarchitecture Linux Performance Modeling PMU Memory Subsystem Firmware Scripting Data Analysis I/O Subsystems +5 more Show less

CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Computer Architecture Physical Design +12 more Show less

STA PrimeTime Tempus TCL Python Perl ICC2 Innovus RTL GDS Spice Signal Integrity Layout Parasitic Extraction Physical Design Timing Closure +10 more Show less

Physical Design Floorplanning RTL SoC STA EMIR Synthesis Place and Route Power Grid Planning Tapeout Layout Design IP Integration +7 more Show less

SPICE RTL Physical Design PLL Standard Cell Optimization Jitter Analysis Circuit Design Verification Hardware Engineering +4 more Show less

Synthesis Place and Route STA TCL Python Perl CSS HTML CGI Data Analytics CPU Design Automation +7 more Show less

Physical Design SPICE RTL Standard Cell Optimization PLL Circuit Design Verification Jitter Measurement Hardware Engineering +4 more Show less

C C++ Python Java Firmware Ubuntu Server RHEL SUSE Windows Server x86 ARM64 RISC-V BIOS UEFI BMC Firmware Test Automation Validation +12 more Show less

CPU Architecture SoC Architecture x86 Arm Accelerated Computing AI Infrastructure Silicon Engineering System Architecture Platform Architecture +4 more Show less

Linux Kernel ARM64 PCIe ACPI CXL Virtualization Memory Management Device Drivers Scheduling Networking Filesystems SoC Architecture Firmware +8 more Show less

x86 Post-Silicon Validation SoC PCIE CXL Coherent Interconnects Python C/C++ Linux Windows DFx Emulation Automation Power Management Memory +10 more Show less