SoC Performance Architect

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXHillsboro, ORSan Diego, CA
Salary
$147,900–$221,900 / yr
Posted
33 days ago
Freshness
Confirmed live today
Closes
Mar 23, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $220k
This role $185k
$132k $293k
below market most similar roles pay here above market

This role pays less than 77% of similar roles. Most pay $190,000–$250,000 — the blue band above. At the midpoint, this role pays about $185k versus about $220k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SoC Performance Architect

JOB TITLE: SoC Performance Architect (Server CPU) - PhD New Grads Welcome! The SoC Performance Architect joins the SoC Architecture team to lead server CPU workload analysis, performance modeling, and optimization across hardware and software. This role focuses on end-to-end system performance for complex server workloads, identifying bottlenecks across the compute stack to drive improvements in CPU, memory, interconnect, I/O, firmware, OS, and compiler behavior. You will build analytical and empirical models, conduct sensitivity studies, and perform bottleneck analysis on CPU cores, cache hierarchies, and memory controllers. Key skills include deep knowledge of CPU microarchitecture, SoC architecture, and OS/compiler behavior. You will use profiling and PMU tools to capture hotspots and CPI breakdowns while developing performance projections for internal and external competitive products within a Linux environment.

What you'll do

  • Define performance methodologies, metrics, and KPI frameworks for consistent workload tracking and feature evaluation.
  • Perform bottleneck analysis across CPU cores, cache hierarchy, memory subsystems, on-chip fabric, and I/O.
  • Use profiling and PMU tools to capture hotspots, call stacks, CPI breakdowns, and microarchitectural stall data.
  • Build analytical and empirical models for workload behavior, scaling, and feature sensitivity.
  • Develop performance projections for internal roadmap products and external competitive products.
  • Identify and prioritize optimization opportunities across hardware, software, firmware, and compiler teams.
  • Communicate findings, tradeoffs, and product implications to technical and executive stakeholders.

What we're looking for

  • PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
  • Bachelor's degree in Electrical Engineering, Computer Science, or related field with 2+ years of Systems Engineering experience.
  • Master's degree in Electrical Engineering, Computer Science, or related field with 1+ year of Systems Engineering experience.
  • 2+ years of experience in system architecture technology areas such as Power Systems or Shared Resource Management.
  • Deep understanding of CPU microarchitecture, including pipelines, out-of-order execution, branch prediction, caches, and performance bottlenecks.
  • Strong knowledge of SoC architecture, including on-chip interconnects, memory controllers, DRAM systems, coherency, and I/O subsystems.
  • Strong understanding of OS and compiler behavior, including scheduling, memory management, and code generation.
  • Hands-on experience with performance analysis tools, Linux server workloads, and scripting for data analysis.
  • Experience with pre-silicon performance modeling, simulation, or trace-based analysis (preferred).
  • Familiarity with PMU-based top-down analysis, CPI decomposition, and sensitivity modeling (preferred).

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