CPU Server Floorplan and Integration Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$147,900–$221,900 / yr
Posted
35 days ago
Freshness
Confirmed live today
Closes
Mar 21, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k
This role $185k
$104k $249k
below market most similar roles pay here above market

This role pays more than 65% of similar roles. Most pay $148,731–$214,000 — the blue band above. At the midpoint, this role pays about $185k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU Server Floorplan and Integration Engineer

The CPU Server Floorplan and Integration Engineer joins the CPU Engineering team to develop high performance, energy efficient server solutions for data center applications. This role involves collaborating with microarchitecture, RTL design, and physical design teams to design, floorplan, and integrate CPU designs while meeting aggressive power, area, and performance goals. Key responsibilities include performing CPU physical design tasks such as floorplanning, Bump/RDL planning, IP integration, power/ground generation, and pin assignment. The engineer will manage chip-level place and route, oversee area optimizations, and develop workflows for chip integration and analysis. Required skills include proficiency in synthesis, place and route, signoff timing/power analysis, and extraction. The role requires expertise in static timing analysis, electromigration, IR drop flows, and low power high-performance design methodologies for large processor and SoC designs.

What you'll do

  • Perform CPU physical design tasks including floorplanning, Bump/RDL planning, and pin assignment.
  • Oversee full chip floorplan, area optimizations, block partitioning, and power/ground generation.
  • Manage chip-level place and route to finalize the CPU database for construction and verification.
  • Coordinate custom layout integration and ensure designs are validated for functional and electrical robustness.
  • Develop workflows for chip integration and analysis.
  • Collaborate with external teams to fulfill IP technical and delivery requirements.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant work experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of relevant work experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • Proficiency in synthesis, place and route, and signoff timing/power analysis.
  • Expertise in block-level implementation, full chip floorplanning, and power grid planning.
  • Skilled in physical design, integration, and verification of large processor and system-on-chip (SoC) designs.
  • In-depth understanding of extraction, static timing analysis (STA), and electromigration and IR drop (EMIR) flows.
  • Experience in deep submicron process technology nodes (preferred).

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