CPU Server Floorplan and Integration Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$142,200–$213,400 / yr
Posted
66 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 3, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $166k
This role $178k
$103k most similar roles pay here $225k

This role pays more than 70% of similar roles. Most pay $144,350–$187,850 — the shaded band above. At the midpoint, this role pays about $178k versus about $166k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · CPU Server Floorplan and Integration Engineer

As a CPU Server Floorplan and Integration Engineer on the Data Center team, you will develop high-performance, energy-efficient server solutions for data center applications. You will collaborate with microarchitecture, RTL design, and physical design teams to floorplan and integrate CPU designs while meeting aggressive power, area, and performance goals. Your daily responsibilities include performing physical design tasks such as block partitioning, Bump/RDL planning, IP integration, power grid generation, and pin assignment. You will also manage chip-level place and route, coordinate custom layout integration, and develop workflows for chip integration and analysis. The role requires expertise in synthesis, place and route, signoff timing and power analysis, and EMIR flows. You must possess a strong understanding of circuit and layout design principles, low power methodologies, and deep submicron process technology nodes to solve complex hardware challenges.

What you'll do

  • Perform CPU physical design tasks including floorplanning, Bump/RDL planning, and power/ground generation.
  • Execute block partitioning, area optimizations, and pin assignments for full chip designs.
  • Manage chip-level place and route processes to finalize the CPU database for construction and verification.
  • Coordinate custom layout integration and ensure designs are validated for functional and electrical robustness.
  • Develop specialized workflows for chip integration and analysis.
  • Integrate IP components while meeting specific technical and delivery requirements from external teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2+ years of relevant experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 1+ year of relevant experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Proficiency in synthesis, place and route, and signoff timing/power analysis.
  • Expertise in block-level implementation, full chip floorplanning, and power grid planning.
  • Experience in physical design, integration, and verification of large processor and SoC designs.
  • In-depth understanding of extraction, static timing analysis (STA), and electromigration and IR drop (EMIR) flows.
  • Knowledge of low power and high-performance design methodologies and circuit/layout design principles.

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