CPU Server FV CLP STA Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$147,900–$221,900 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Mar 7, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k
This role $185k
$139k most similar roles pay here $235k

This role pays less than 56% of similar roles. Most pay $161,487–$216,250 — the shaded band above. At the midpoint, this role pays about $185k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Server FV CLP STA Engineer

The CPU Sever FV/CLP/STA engineer joins the CPU Engineering team to perform critical tasks involving complex data path oriented multi-million gate synthesis and physical synthesis. The role involves developing constraints for multi-clock domains in hierarchical or flat timing analysis, performing structural power checks using CLP, and conducting formal verification with a focus on debugging issues and aborts. Day-to-day responsibilities include pre-layout STA, analyzing timing reports, generating timing ECOs, and evaluating trade-offs for timing, area, power, and congestion. The candidate will utilize tools such as DC, Genus, and Fusion Compiler while utilizing TCL scripting for synthesis and STA tasks. This position addresses technical challenges in high-performance processor design by ensuring robust timing closure and power integrity across complex integrated circuits within the CPU domain.

What you'll do

  • Perform multi-million gate synthesis for complex data path oriented designs.
  • Develop constraints for multi-clock domains in hierarchical and flat timing analysis.
  • Execute multi-power domain synthesis and perform structural power checks using CLP.
  • Conduct formal verification and debug issues or aborts to resolve technical problems.
  • Perform pre-layout STA, analyze timing reports, and generate timing ECOs.
  • Analyze trade-offs and determine recipes for timing, area, power, and congestion.
  • Utilize TCL scripting for tasks involving synthesis and static timing analysis.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of relevant experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • Experience handling complex data path oriented Multi-million gate synthesis using tools like DC, Genus, or Fusion Compiler.
  • Experience developing constraints for multi-clock domains hierarchical/flat timing analysis and performing pre-layout STA.
  • Knowledge of multi-power domain synthesis, structural power checks using CLP, and analyzing trade-offs for timing, area, power, and congestion.
  • Hands-on experience in Formal verification with strong debugging skills to resolve issues and aborts.
  • Exposure to TCL scripting for Synthesis/STA and knowledge of Hierarchical STA with Hyperscale (preferred).

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