CPU Server Physical Design Timing Engineer
Qualcomm
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How this pay compares to similar roles
This role pays less than 64% of similar roles. Most pay $169,337–$246,000 — the blue band above. At the midpoint, this role pays about $185k versus about $208k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 575 open roles on FindRole.
Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.
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At a glance
The CPU Server FV/CLP/STA engineer joins the CPU Engineering group to handle complex data path oriented multi-million gate synthesis. The role involves planning, designing, and optimizing electronic systems while performing physical synthesis using tools like DC, Genus, and Fusion Compiler. Key responsibilities include developing constraints for multi-clock domains, performing hierarchical and flat timing analysis, and conducting multi-power domain synthesis with structural power checks using CLP. The engineer must perform formal verification, debug issues, and conduct pre-layout STA to analyze timing reports and generate timing ECOs. Required skills include TCL scripting for synthesis and STA, and the ability to analyze trade-offs for timing, area, power, and congestion. The work focuses on resolving technical issues independently within a cross-functional hardware engineering environment.
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