CPU Synthesis CAD Engineer
Qualcomm
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How this pay compares to similar roles
This role pays less than 56% of similar roles. Most pay $161,487–$216,250 — the shaded band above. At the midpoint, this role pays about $185k versus about $189k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
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At a glance
The CPU Sever FV/CLP/STA engineer joins the CPU Engineering team to perform critical tasks involving complex data path oriented multi-million gate synthesis and physical synthesis. The role involves developing constraints for multi-clock domains in hierarchical or flat timing analysis, performing structural power checks using CLP, and conducting formal verification with a focus on debugging issues and aborts. Day-to-day responsibilities include pre-layout STA, analyzing timing reports, generating timing ECOs, and evaluating trade-offs for timing, area, power, and congestion. The candidate will utilize tools such as DC, Genus, and Fusion Compiler while utilizing TCL scripting for synthesis and STA tasks. This position addresses technical challenges in high-performance processor design by ensuring robust timing closure and power integrity across complex integrated circuits within the CPU domain.
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