CPU Server FV/CLP/STA Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$147,900–$221,900 / yr
Posted
29 days ago
Freshness
Confirmed live today
Closes
Mar 27, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $208k
This role $185k
$134k $277k
below market most similar roles pay here above market

This role pays less than 64% of similar roles. Most pay $169,337–$246,000 — the blue band above. At the midpoint, this role pays about $185k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU Server FV/CLP/STA Engineer

The CPU Server FV/CLP/STA engineer joins the CPU Engineering group to handle complex data path oriented multi-million gate synthesis. The role involves planning, designing, and optimizing electronic systems while performing physical synthesis using tools like DC, Genus, and Fusion Compiler. Key responsibilities include developing constraints for multi-clock domains, performing hierarchical and flat timing analysis, and conducting multi-power domain synthesis with structural power checks using CLP. The engineer must perform formal verification, debug issues, and conduct pre-layout STA to analyze timing reports and generate timing ECOs. Required skills include TCL scripting for synthesis and STA, and the ability to analyze trade-offs for timing, area, power, and congestion. The work focuses on resolving technical issues independently within a cross-functional hardware engineering environment.

What you'll do

  • Perform multi-million gate synthesis for complex data path oriented designs.
  • Develop constraints for multi-clock domain hierarchical and flat timing analysis.
  • Execute multi-power domain synthesis and perform structural power checks using CLP.
  • Conduct formal verification and debug issues or aborts independently.
  • Perform pre-layout STA, analyze timing reports, and generate timing ECOs.
  • Analyze trade-offs and recipes for timing, area, power, and congestion.
  • Write TCL scripts for use in Synthesis and STA processes.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant work experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of relevant work experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • Experience in handling complex data path oriented Multi-million gate synthesis using tools like DC, Genus, or Fusion Compiler.
  • Experience in developing constraints for multi-clock domains hierarchical/flat timing analysis.
  • Working knowledge in multi-power domain synthesis and structural power checks using CLP.
  • Hands-on experience in Formal verification with strong debugging skills for resolving issues/aborts.
  • Working knowledge in Pre-layout STA, analyzing timing reports, and generating timing ECOs.
  • Knowledge of analyzing trade-offs and recipes for timing, area, power, and congestion.
  • Exposure to TCL scripting for usage in Synthesis/STA.
  • Knowledge on Hierarchical STA with Hyperscale (preferred).

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