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PCB Design Oscilloscopes Multimeters Logic Analyzers Linux Windows GPU Tegra System Design +4 more Show less

React TypeScript Figma Design Systems Style Dictionary Storybook CI/CD CSS Custom Properties pnpm Turborepo Changesets SemVer React Aria DTCG Design Tokens Monorepos Visual Regression Testing +11 more Show less

React TypeScript Figma Design Systems Style Dictionary Storybook CI/CD Accessibility ARIA CSS Custom Properties pnpm Turborepo Changesets SemVer Radix React Aria DTCG Monorepos Linting +14 more Show less

Digital Signal Processing MATLAB C/C++ Serdes RTL Firmware Communication Theory PAM FEC CDR PCIe IEEE 802.3 OIF Signal Processing Algorithms +9 more Show less

Signal Integrity FPGA Xilinx Altera HDL SERDES DDR3 DDR4 DDR5 I2C JTAG UART SPI PCIe eMMC Linux Mentor Graphics DxDesigner Vivado Quartus HyperLynx Sigrity PowerSI PowerDC ADS Ansys HFSS SPICE Python Perl +22 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling Coherent Interconnects +9 more Show less

Python Data Pipelines LLM System Software Silicon Bring-up Productization Engineering DFT DFP ATE SLT BLT L10+ +7 more Show less

Digital Signal Processing MATLAB C/C++ Serdes RTL Firmware Communication Theory PAM FEC CDR IEEE 802.3 OIF PCIe Signal Processing Algorithms +9 more Show less

Android Kotlin Jetpack Compose UI Architecture Design Systems Accessibility Performance Optimization Instruments Component Libraries Frontend Infrastructure +5 more Show less

React TypeScript Python Node.js Claude Code MCP Storybook HTML CSS CI/CD Axe GitHub Figma WCAG 2.2 AA data-visualization OutSystems +11 more Show less

React TypeScript Node.js Design Systems Vitest React Testing Library Frontend Architecture UI Component Libraries +3 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification Pre-silicon Testbench Development Computer Architecture Arbitration Scripting Data Structures Algorithms RTL Performance Verification +10 more Show less