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Active Keyword: Senior RTL Engineer Remove filter Clear all

9 of up to 20 (filtered)

Senior ASIC RTL Engineer

Cisco

San Jose, CA +1 6 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug Power Optimization Power Estimation
7+ yrs exp Hybrid
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Senior Engineer, GPU RTL Design

Samsung Electronics

Austin, TX +1 18 days ago $124,000–$208,400
Actively hiring Confirmed live today Trusted Below market
Verilog SystemVerilog RTL Design ASIC Design GPU Architecture Microarchitecture Synthesis Linting Timing Analysis SoC Hardware Design PPA Digital Design Cache Design Memory Systems Datapath Control Logic
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Senior Staff Engineer, GPU RTL Firmware

Samsung Electronics

Austin, TX 18 days ago $180,200–$297,200
Actively hiring Confirmed live today Trusted Above market
Firmware Development C C++ Assembly RISC-V Verilog SystemVerilog RTL Design ASIC Flow Vulkan OpenGL Direct3D OpenCL GPU Architecture SoC Architecture Bring-up Debug
10+ yrs exp
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Senior Engineer, GPU RTL Design - Pixel Pipe

Samsung Electronics

San Jose, CA 18 days ago $124,000–$208,400
Actively hiring Confirmed live today Trusted Below market
Verilog SystemVerilog RTL Design GPU Architecture SoC ASIC Design Flow Linting Synthesis Timing Analysis Microarchitecture PPA Digital Design Debug Simulation
2+ yrs exp
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Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA 20 days ago $155,000–$195,000
Actively hiring Confirmed live yesterday Trusted Below market
FPGA RTL Digital Signal Processing Vivado Xilinx MATLAB Hardware Verification Logic Analyzers ASIC Simulation Test Bench Development Timing Closure MIMO MANET
6+ yrs exp Hybrid
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Senior Full-Chip RTL Integration Engineer

Nvidia

Santa Clara, CA +1 20 days ago $168,000–$264,500
Actively hiring Confirmed live today High trust Above market
RTL Integration SystemVerilog UVM ASIC SoC DFT Python Perl Tcl Shell Scripting CDC RDC Lint ATPG MBIST LBIST JTAG UPF Synopsys Cadence Siemens
8+ yrs exp Hybrid
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Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor

San Jose, CA 67 days ago $138,000–$206,000
Actively hiring Confirmed live yesterday High trust Below market
Verilog SystemVerilog RTL PCIe CXL UCIe SoC Microarchitecture Python Tcl Perl AXI ACE CHI APB IP-XACT NoC AI/ML Agentic AI Chiplet
5+ yrs exp
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Senior RTL Engineer, Memory Centric Computing

Samsung Semiconductor

San Jose, CA 69 days ago $138,000–$206,000
Actively hiring Confirmed live today High trust Below market
Verilog System Verilog HLS RTL Microarchitecture Computer Architecture Memory Controller NoC Interconnect IP SOC Integration AI/ML Pipelining Data Compression Hardware Architecture
5+ yrs exp
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