Senior Package Layout Engineer, Hardware

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CANVORAZWA
Salary
$136,000–$212,750 / yr
Posted
9 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $174k
$126k most similar roles pay here $228k

This role pays less than 65% of similar roles. Most pay $167,975–$216,250 — the shaded band above. At the midpoint, this role pays about $174k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Package Layout Engineer, Hardware

As a Senior Package Layout Engineer - Hardware, you will join the Layout team to design and develop sophisticated, detailed layouts of IC substrates for products. You will collaborate with Technical Package Leads and various design teams to implement high speed/density ASIC packages, perform substrate breakout patterns, and optimize package pinouts while managing system level trade-offs. Your daily responsibilities include performing package routing, placement, stack-up, reference plane, and power distribution using Cadence APD or SiP tool suites. You will also conduct design feasibility studies for size, cost, and performance, while developing symbols and CAD library databases to improve productivity. Required skills include experience with PCB layout of graphics cards or motherboards, HDI designs, wire bond and flip chip packages, high-speed signal integrity practices, and proficiency in tools like Virtuoso, Calibre, and Valor.

What you'll do

  • Implement high speed and high density ASIC packages.
  • Perform substrate breakout patterns for ASIC packages.
  • Optimize package pinout based on system level trade-offs of pin assignments.
  • Execute package routing, placement, stack-up, reference plane, and power distribution using Cadence tools.
  • Conduct design feasibility studies to evaluate size, cost, and system performance goals.
  • Develop symbols and CAD library databases using Cadence APD design tools.
  • Create methodologies to improve layout productivity.

What we're looking for

  • Hold a B.S. in Electrical Engineering or equivalent experience.
  • Have 5+ years of experience in PCB Layout for graphics cards, motherboards, line cards, or related technologies.
  • Possess proven experience in substrate layout of wire bond and flip chip packages.
  • Demonstrate significant background with Cadence APD, SiP, or other PCB layout tools including Constraint Manager.
  • Maintain a solid understanding of high-speed design signal integrity practices.
  • Experience with HDI designs is preferred.
  • Experience with Virtuoso and Calibre is a plus.
  • Proficiency in using Valor is helpful.

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